DMI and SOC

[Phantasm]

Hi guys,

I've been googling around for a while now trying to find out about SOC (System-on-a-chip)

Looks like the new skylake chips have 4 lanes of DMI access from the PCH to the cpu/ram. So... If you want to load data from an M.2 Card or a PCI-E raid card, and load it into ram, youre limited by 4 lanes of DMI.

I'm not exactly sure what that means but I read a review somewhere of the new skylake chips critizising them for not being very future proof with respect to the new storage technology, namely M.2 and NVME drives... basically it said that with amount of data being pushed through an M.2 drive alone, it would be sufficient to saturate the DMI 3.0 linkon the skylake chips, and if not, definitely if you have an NVME drive along side an M.2 drive...

First question: Is that true?

I'm concerned as my new pc build I have planned includes a rather beefy PCIE-E raid card along side an M.2 os drive..

Second question...

I noticed that a new Xeon chip has something called SOC. Basically the Xeon D chips (Xeon D-1548 for example) has SOC archetecture which basically means the whole northbridge is incorporated in to the CPU chip (cool!) So... if i understand things correctly, NVME/PCIE Raid/ M.2 will communicate to the CPU over the pcie lanes (of which there should be plenty)
but the question is, will there still be a DMI bottleneck (albeit on the cpu this time)? also, what is the bandwidth limit of the dmi link on these chips?

Third question. I assume server chips have more DMI/QPI (are those things different flavours of the same thing?) lanes as they would need to deal with more data bandwidth... is that right?

TLDR: What chip do i want to buy if I'm going to be transferring 6GB/s from pcie storage into ram

Thanks for your time,