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what is Intel WatchDog Timer
- Thread starter XdVeLoPeX
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drescherjm
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I thought watchdog timer was a method used in servers to detect a hung machine. Basically the system will issue periodic interrupts via a timer and if the OS did not respond (within some time frame ) it will assume the system is hung and hit the reset button.
xSystemFailurex
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Adjust your tinfoil hat 32 degrees south.
/fixed
/fixed
Ruoh
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What the hell is wrong with your keyboard?
defaultluser
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A watchdog timer is an independent counter that increments on each clock edge regardless of the state of the main CPU.
A watchdog timer can be configured to reset the machine if the count reaches a certain value. It is up to the main CPU software to reset the counter periodically. This means that if the CPU gets locked-up, the watchdog timer will hit it's limit and reset the machine.
A watchdog timer can be configured to reset the machine if the count reaches a certain value. It is up to the main CPU software to reset the counter periodically. This means that if the CPU gets locked-up, the watchdog timer will hit it's limit and reset the machine.
IntelEnthusiast
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ftp://download.intel.com/design/chipsets/applnots/29227301.pdf
Watchdog Timer Objectives
There are many reasons why a computer might cease to operate correctly. A few of the possible
reasons include:
• A software error can cause the Operating System (OS) to stop scheduling tasks.
• A software error may leave certain interrupts disabled or masked, preventing other
software from continuing until an interrupt is completed.
• A hardware error may prevent data from flowing properly within the system.
• A hardware error can halt operation of the CPU.
A key assumption is required: a correctly functioning OS can schedule tasks to be run on a
periodic basis. If a task is not able to be completed within a predetermined bounded time, a
separate monitoring circuit can conclude that the system is malfunctioning. The monitoring
circuit, often called a Watchdog Timer (WDT), must be able to independently track the
completion of a task within its time limit. It must be able to do so independently of the OS’s state,
the CPU’s state or ability to run the OS, or the state of any other hardware device that might lead
to a system malfunction.
Upon determining that its time limit has been reached, the WDT circuit concludes that an error has
occurred and may take a variety of corrective actions. For example, it may attempt to generate a
non-maskable interrupt, reset the platform, or even force the shut-down of the platform. The WDT
may react in different ways depending on the other factors, such as measured activity from the
CPU or reception of interrupts from peripherals.
Working in conjunction with an appropriate BIOS and OS, the WDT enables the platform to
detect and take corrective action from a variety of errors. The function is intended to meet the
following objectives:
• Detect and recover from either hardware or software errors that lock up the platform.
• Allow a programmable amount of time to pass before concluding that the hardware has
malfunctioned.
• Support a programmable response to the lockup, including resetting the platform or
shutting it down.
• Minimize software overhead required to manage the WDT.
• Provide information for recovery software to determine why the platform was reset (i.e.
reset was due to WDT expiration).
Long term, the platform should be able to detect and recover from lockups that occur during the
BIOS to OS handoff. The software mechanisms required to enable this have not been defined as
of this revision of this document. It is anticipated that a future revision may document these
mechanisms.
In otherword this has nothing to do with stopping you from hitting 5GHz.
Watchdog Timer Objectives
There are many reasons why a computer might cease to operate correctly. A few of the possible
reasons include:
• A software error can cause the Operating System (OS) to stop scheduling tasks.
• A software error may leave certain interrupts disabled or masked, preventing other
software from continuing until an interrupt is completed.
• A hardware error may prevent data from flowing properly within the system.
• A hardware error can halt operation of the CPU.
A key assumption is required: a correctly functioning OS can schedule tasks to be run on a
periodic basis. If a task is not able to be completed within a predetermined bounded time, a
separate monitoring circuit can conclude that the system is malfunctioning. The monitoring
circuit, often called a Watchdog Timer (WDT), must be able to independently track the
completion of a task within its time limit. It must be able to do so independently of the OS’s state,
the CPU’s state or ability to run the OS, or the state of any other hardware device that might lead
to a system malfunction.
Upon determining that its time limit has been reached, the WDT circuit concludes that an error has
occurred and may take a variety of corrective actions. For example, it may attempt to generate a
non-maskable interrupt, reset the platform, or even force the shut-down of the platform. The WDT
may react in different ways depending on the other factors, such as measured activity from the
CPU or reception of interrupts from peripherals.
Working in conjunction with an appropriate BIOS and OS, the WDT enables the platform to
detect and take corrective action from a variety of errors. The function is intended to meet the
following objectives:
• Detect and recover from either hardware or software errors that lock up the platform.
• Allow a programmable amount of time to pass before concluding that the hardware has
malfunctioned.
• Support a programmable response to the lockup, including resetting the platform or
shutting it down.
• Minimize software overhead required to manage the WDT.
• Provide information for recovery software to determine why the platform was reset (i.e.
reset was due to WDT expiration).
Long term, the platform should be able to detect and recover from lockups that occur during the
BIOS to OS handoff. The software mechanisms required to enable this have not been defined as
of this revision of this document. It is anticipated that a future revision may document these
mechanisms.
In otherword this has nothing to do with stopping you from hitting 5GHz.