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“It's anyone's guess what "BFC" abbreviates; Intel probably has some clever marketing name for that acronym, such as "big fusion cache," and of course gamers would know what "F" word substitute to use here.
The idea behind bLLC is the same as AMD had for 3D V-Cache. AMD discovered that enlarging the L3 cache of the processor can significantly improve gaming performance of the processor as it places more of the fast-moving game data, such as textures within 1/6th the latency of DRAM. While AMD stacks a slab of L3 cache memory on top of its CCD, over the central region with the on-die L3 cache to achieve a contiguously addressable cache block; Intel may use a different approach, such as having a cache tile sitting beside the Compute tile, with the ringbus of the compute-complex being extended to it, or short-terminating in the absence of it.“
Source: https://www.techpowerup.com/353663/intel-refers-to-its-3d-v-cache-analog-as-bfc
The idea behind bLLC is the same as AMD had for 3D V-Cache. AMD discovered that enlarging the L3 cache of the processor can significantly improve gaming performance of the processor as it places more of the fast-moving game data, such as textures within 1/6th the latency of DRAM. While AMD stacks a slab of L3 cache memory on top of its CCD, over the central region with the on-die L3 cache to achieve a contiguously addressable cache block; Intel may use a different approach, such as having a cache tile sitting beside the Compute tile, with the ringbus of the compute-complex being extended to it, or short-terminating in the absence of it.“
Source: https://www.techpowerup.com/353663/intel-refers-to-its-3d-v-cache-analog-as-bfc