AMD Helios Architecture Deep Dive: The Power of AMD’s Hardware

“Final Words​

Wrapping up our look at the AMD Helios architecture, if there is only one thing to take away from the system’s design, it is probably the impact of networking hardware on the larger rack-scale system. Not only is it a core component of building a rackscale system, but it is also the single greatest differentiator between Helios and earlier clusters based on MI3xx. Networking hardware is integrated throughout the system, from discrete NICs and DPUs to massive switch trays to UALoE links baked into the MI455X GPUs themselves. To be sure, Helios is a testament to many different AMD teams, but it is the integration of networking that has enabled AMD to finally scale up to this level – and it will be networking that will let them scale up further in successive generations, as well.

On which note, besides AMD’s ambitions for Helios in the immediate future, the rackscale system is also slated to be the first in an ongoing series of rackscale systems from the company. With AMD operating on a yearly cadence for its datacenter GPUs (and to a lesser extent with its DC CPU), the company is also putting Helios on an annual cadence.

Later next year, AMD will be releasing its first follow-up rackscale system, tentatively titled Helios 500. The 500 will combine AMD’s EPYC “Verano” CPUs (Zen 6 with LPDDR) with AMD’s next-generation Instinct MI500 GPUs. It will also incorporate new Pensando NICs and DPUs, which are currently going under the codenames “Como” and “Monza”. Unlike last year’s Helios preview, this year AMD is not disclosing any significant specifications about the next-generation rackscale system this far in advance, and for now, the bulk of AMD’s energy and attention is on Helios.

On that note, with all of Helios’s constituent components now in production, so are the full Helios racks. According to AMD, the first production Helios racks will ship to customers in Q3 of this year, with AMD continuing to ramp up production through the second half of next year. So while Helios’s production kicking off is an important moment for AMD, it is just the next step in bringing the rackscale system to market. Nonetheless, exciting times are ahead for AMD.“

Source: https://www.servethehome.com/amd-helios-architecture-deep-dive-amd-broadcom-hardware-combined/5/

erek said:

“Final Words​

Wrapping up our look at the AMD Helios architecture, if there is only one thing to take away from the system’s design, it is probably the impact of networking hardware on the larger rack-scale system. Not only is it a core component of building a rackscale system, but it is also the single greatest differentiator between Helios and earlier clusters based on MI3xx. Networking hardware is integrated throughout the system, from discrete NICs and DPUs to massive switch trays to UALoE links baked into the MI455X GPUs themselves. To be sure, Helios is a testament to many different AMD teams, but it is the integration of networking that has enabled AMD to finally scale up to this level – and it will be networking that will let them scale up further in successive generations, as well.

On which note, besides AMD’s ambitions for Helios in the immediate future, the rackscale system is also slated to be the first in an ongoing series of rackscale systems from the company. With AMD operating on a yearly cadence for its datacenter GPUs (and to a lesser extent with its DC CPU), the company is also putting Helios on an annual cadence.

Later next year, AMD will be releasing its first follow-up rackscale system, tentatively titled Helios 500. The 500 will combine AMD’s EPYC “Verano” CPUs (Zen 6 with LPDDR) with AMD’s next-generation Instinct MI500 GPUs. It will also incorporate new Pensando NICs and DPUs, which are currently going under the codenames “Como” and “Monza”. Unlike last year’s Helios preview, this year AMD is not disclosing any significant specifications about the next-generation rackscale system this far in advance, and for now, the bulk of AMD’s energy and attention is on Helios.

On that note, with all of Helios’s constituent components now in production, so are the full Helios racks. According to AMD, the first production Helios racks will ship to customers in Q3 of this year, with AMD continuing to ramp up production through the second half of next year. So while Helios’s production kicking off is an important moment for AMD, it is just the next step in bringing the rackscale system to market. Nonetheless, exciting times are ahead for AMD.“

Source: https://www.servethehome.com/amd-helios-architecture-deep-dive-amd-broadcom-hardware-combined/5/

Click to expand...

Intel's response? Do I hear crickets?

AMD Instinct MI455X Deep Dive: CDNA 5 Marks The Next Era of Instinct​

By Ryan Smith - August 12, 2026


The CDNA 5 architecture also brings with it a huge revamp of AMD’s core GPU architecture.

Essentially borrowing and enhancing the core compute architecture of AMD’s RDNA line of GPUs, which introduced a similar, SIMD32-based approach to ALU organization, CDNA 5 is the biggest change to AMD’s server GPU architectures since the Instinct line was launched almost a decade ago.

A Brief History of CDNA & GCN​

Without getting too deep into the weeds of history here, the first four iterations of AMD’s CDNA architecture can all trace their origins back to AMD’s Vega architecture, which itself was the fifth and final mainstream iteration of AMD’s Graphics Core Next (GCN) architecture. First introduced by AMD in 2012 for consumer cards and then iterated upon and improved many times since then, the fundamental GCN architecture has been the backbone of AMD’s server GPUs for well over a decade at this point.

After branching from AMD’s mainstream chips in 2017 with the Vega (GCN5) architecture, each iteration of CDNA since then has added many new features to AMD’s GPU compute architecture. However, even with all of those changes, they were all fundamentally extensions of GCN and its 16-slot ALU structure. Internally, all of these resulting chips were part of what AMD calls their GFX9 architecture, which is the architecture classification for the Vega architecture and all of its derivatives.

But as time passes, all good things must come to an end. And so the end has come for GCN and the GFX9 architecture. AMD started to leave behind GCN in 2019 with the RDNA family of architectures for graphics chips, and now CDNA is doing the same for server accelerators, syncing up with RDNA to inherit many of its fundamental changes that have underpinned AMD’s graphics GPU architectures since then.

The single biggest change brought with CDNA 5 is that the underlying ALU/SIMD structure and execution model is widely different. Previously, AMD’s thread wavefronts were 64 threads wide, commonly referred to as Wave64. Each 64-thread wavefront would then occupy a 16-slot SIMD (SIMD16) for four cycles, with the SIMD processing a quarter of the wavefront in each cycle.

The combination of Wave64 executing on top of a SIMD16 had its drawbacks, however: to fill a wavefront, the shader compiler (or human author) needed to be able to find 64 threads that could be grouped together, and there would always be that 4-cycle instruction latency. High concurrency is very efficient in terms of transistor usage (and is the same basic principle as tensor/matrix cores), but filling that kind of concurrency can be difficult.

Modern CDNA Gets Wider: Wave32 + SIMD32​

Ultimately, AMD decided that the drawbacks to Wave64 + SIMD16 were too much in practice, and that they were not reaching the kind of high utilization/high performance that they wanted from GCN.

To remedy that, in 2019 for the first RDNA architecture (GFX10), AMD radically revised their GPU architecture. The size of wavefronts was cut down from 64 threads to 32 threads wide (Wave32), and the size of the internal SIMDs was expanded from 16 ALUs wide to 32 ALUs wide (SIMD32). Now, AMD’s GPU architecture could execute a single instruction from an entire wavefront in a single cycle. Among other benefits, this aligned AMD’s wavefront size with NVIDIA’s, reduced instruction latency, and improved SIMD utilization (and thus higher effective IPC rates) by allowing for smaller groupings of threads.

CDNA 5 architecture AMD is making a very similar shift. Gone are the SIMD16s and the native Wave64 wavefronts (though emulation is supported). In its place are SIMD32s and an emphasis on Wave32 wavefronts.

Click to expand...

the vector units were not the only enhancements in the CDNA 5 architecture. The matrix units, which like the vector units are packed 4 to a WGP, were given a throughput enhancement as well. At the baseline, each matrix unit can now process at least twice as many operations per clock with large tensors, effectively making each matrix unit twice as wide. Furthermore, for FP4 and FP8 in particular, AMD has improved performance there by even more, allowing CDNA 5 to process 4x as many operations per clock.

Consequently, while the high-level hardware figures do not necessarily indicate it, AMD has greatly enhanced the raw throughput (and really, the raw number of ALUs) within each one of their fundamental WGPs, and this is what is driving so much of MI455X’s peak compute throughput improvements

https://www.servethehome.com/amd-instinct-mi455x-deep-dive-cdna-5-marks-the-next-era-of-instinct/

philb2 said:

Intel's response? Do I hear crickets?

Click to expand...

You’ve got it backwards.
This is AMD’s response to the Xeon Scalable platform.

Lakados said:

You’ve got it backwards.
This is AMD’s response to the Xeon Scalable platform.

Click to expand...

philb2 said:

Intel's response? Do I hear crickets?

Click to expand...

Best I can do is the i740