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Prompt to tape out: 1.5 GHz RISC-V CPU

erek

erek

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"Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU​

Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC."
Click to expand...

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Source: https://blog.adafruit.com/2026/03/2...utonomous-ai-agent-builds-1-5-ghz-risc-v-cpu/
 
Any idiot can implement a chip given ideal constraints (no hard speed, power, area, testability, etc. requirements)
It's also telling that the floorplans shown are all square (ideal AR to evenly distribute metal routing resources)

On another note, ChipAgents is the DLSS5 of the chip design world

<- Dayjob
 
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Getting from a short prompt to a tape-out ready design in like half a day sounds insane on paper, but I’m with the skepticism here. Hitting ~1.5 GHz under ideal conditions is one thing, doing it under real PPA constraints is a totally different game. Still, even as a proof of concept, automating RTL to GDSII like that could seriously change how early-stage chip design gets done.
 
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