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As DRAM cells continues to shrink and frequencies rise, individual memory cells have become more vulnerable to interference from neighboring cells. So called "row hammer" errors arise in cells adjacent to rows of repeatedly accessed memory, leading to data corruption and, in some cases, potential exploit paths. While manufacturers have implemented workarounds to mitigate the issue over the last few years, researchers from the Indian Institute of Technology and Applied Materials think they found a complete solution manufacturers can bake straight into their memory chips. Embedding metallic nanoparticles between individual memory cells would create an a "energy valley" that isolates the cells from each other, the researchers say. Cells rapidly switching on and off wouldn't create any significant interference in adjacent cells. They even speculate that the technique could be applied to traditional logic cells, like those used in CPUs and GPUs. As chip manufacturers face more and more trouble moving to smaller nodes, and as some designers look at integrating eDRAM straight into logic chips, techniques like this could be essential in the production of faster, denser memory in the future.
The researchers believe that the introduction of nanoparticles into DRAM gate stack engineering is a novel technique that could even be extended to digital logic technologies. In looking ahead to how this technique could actually become part of DRAM, the researchers have suggested possible steps whereby nanoparticles could be introduced selectively.
Arvind added: "It will require additional steps in the conventional DRAM fabrication process flow. Memory manufacturers such as Samsung, Micron, Hynix, and others may find this idea [to be] an interesting process solution for nanoparticle engineered gate stacks at a low cost."
The researchers believe that the introduction of nanoparticles into DRAM gate stack engineering is a novel technique that could even be extended to digital logic technologies. In looking ahead to how this technique could actually become part of DRAM, the researchers have suggested possible steps whereby nanoparticles could be introduced selectively.
Arvind added: "It will require additional steps in the conventional DRAM fabrication process flow. Memory manufacturers such as Samsung, Micron, Hynix, and others may find this idea [to be] an interesting process solution for nanoparticle engineered gate stacks at a low cost."