Recent content by mrcmtl

Is it possible to design a scheduler inside the chip itself so that it can manage the threads on its own? For example, would it be possible to shut down one integer core per module when 4 or less threads are being executed and then enable them as needed when thread count increases?

Seeing as how Bulldozer's L3 cache is slow to access and it is also the first layer for sharing data between modules, wouldn't a fast shared L2 be more relevant?