Recent content by c0d1f1ed

Don't confuse cores and threads to be the only form of parallelism. There's Instruction Level Parallelism (ILP), Data Level Parallelism (DLP), and Task Level Parallelism (TLP). Only TLP corresponds to threads in CPUs. CPUs are also very good at extracting ILP. Even though many instructions...

Of course they won't all be Haswell chips on the day of the launch, but the fact remains that a significant market will be created quite rapidly. Also keep in mind that the people most likely to pay for new high performance software are also those who upgrade their hardware early. So developers...

Because it's not an "incredibly" small portion of users, and because of the halo effect. Intel sells a million chips per day. And most software products are considered pretty successful if you can sell a hundred thousand copies. So the market for AVX2 will be very substantial in absolute...

Only this time it's not a small section of the market. AVX2 is nothing like any of the previous instruction set extensions. For the first time in the history of consumer processors, we'll have vector equivalents for each scalar instruction. For instance a single gather instruction can read eight...

Time to get excited! AVX2 is being implemented, today. :cool: Aside from indeed offering a fourfold increase in the peak floating-point throughput over SSE4, it is fundamentally different from any previous instruction set extension because it enables compilers to easily auto-vectorize code...

The pin toy is the key to understanding how this can be compressed. It's indeed not possible to create complex objects using a single pin toy. It only gives you one 'depth surface' for the top. Now imagine having a 'depth surface' for the bottom, left side, right side, front, and back as well...

You can find out yourself using SwiftShader. Note that Unlimited Detail's demo does not appear to be using any advanced shading, while SwiftShader can run Crysis at up to 20 FPS on the latest mainstream CPUs. So in that respect, the UD demo isn't extremely impressive. Modern CPUs pack a lot...

Could you point me to an official statement where Sandy Bridge was claimed to have FMA support? Here's an October 2008 post from an Intel engineer confirming Sandy Bridge not to have FMA support: http://software.intel.com/en-us/forums/showthread.php?t=61121. AMD had planned FMA support for its...

I doubt that. FMA support was a separate CPUID flag in the March 2008 AVX Programming Reference. So it doesn't seem they ever intended to introduce AVX and FMA in the same architecture. And apart from that, FMA also demands higher cache bandwidth. But they already included a second 128-bit...

Without a doubt the most revolutionary thing about AVX2 is the gather instruction support. They borrowed that from the Larrabee project. Even though Larrabee itself has not yet been able to measure up to GPUs (especially at legacy graphics), adding gather support to the CPU makes a lot of sense...

No, Haswell be a "tock", which means it will have significant architectural changes. Ivy Bridge is a "tick+". The plus most likely refers to Tri-Gate technology. Others will move to 22 nm technology without such technology, so Intel will have a significant advantage over just the process...