Why 4 sticks might not work on P965 boards.

BillParrish

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From the P965 application notes for the MCH. emphasis is my addition.

For example, a DDR2-667 DIMM with supported 5-5-5 speed bin timings installed with
a DDR2-533 DIMM with supported 4-4-4 speed bin timings should run at 533 MHz
with supported 4-4-4 speed bin timings. The DDR2-667 DIMM should downshift to
DDR2-533 timings, thus allowing the system to run at 533 MHz with supported 4-4-4
speed bin timings. The DDR2-667 DIMM will only downshift to
DDR2-533, if the timings for DDR2-533 are programmed in the DDR2-667 DIMMs SPD
.


http://download.intel.com/design/chipsets/applnots/31320702.pdf

What does this mean ?
if 2 sticks of X will boot, and 2 sticks of Y will boot, but X and Y will not, put in each pair and find a utility that will read the SPD data. IF they do not share the same JEDEC timings (regardless of what the manuf specs/advertises ) in the SPD tables, you will probally have big problems (but see note at bottom). It also should apply to single sticks or any mismatch of memory in a P965 for that matter.


I imagine a creative bios programmer could get around this, but doubt anyone has taken the time (or bios memory space) to do it.

Sisoft Sandra can read SPDs, cpu-z can too but its buggy and doesnt show EPP all the time, and I doubt EPP counts but dont know for sure.

SPD is serial presence detect (it think) anywho, its a little chip on each memory stick that in addition of some other things, is programmed with the startup timing specifications for the memory stick so that the computer can figure out how to deal with it until the computer get far enough along in the POST/Boot process to be smart enough to figure things out for itself (use your bios settings) .

OK, you are desperate, you absolutely have no other way out, you dont mind if you mess up a stick(s) and it cant be returned, you have a lot of experience and you know what SPD chips are, and JEDEC standards. You might could try this utility, dont bitch at me if you fark up, I am saying it exists, I am not saying you should use it. For goodness sake read the whole thread, twice.
http://www.xtremesystems.org/forums/showthread.php?t=123624
 
I dont get it? I was running 4 sticks both pc5400 but different bin timings, kingston 5-5-5-15 and crucial 3-3-3-8...... I run it at 420fsb 4-4-4-12 and didnt have a problem......
 
it's roughly akin to how amd says the max speed with 4 sticks is ddr333 on 939 platforms. we all know it usually clocks higher, but sometimes it doesn't.

props for the investigative work Bill :D
 
I dont get it? I was running 4 sticks both pc5400 but different bin timings, kingston 5-5-5-15 and crucial 3-3-3-8...... I run it at 420fsb 4-4-4-12 and didnt have a problem......

hmm well I think
a) you got lucky
b) you got lucky
c):D :cool:

Have you looked at the actual SPD chip programming or are you just quoting manuf specs ? (since the 3 3 3 8 is not per JEDEC I doubt its the SPD setting and I am concerned you quite get what the Intel spec was saying.) It is highly likely the SPD chips for both kinds of sticks were programmed for the JEDEC 5 5 5 15 timing which allowed the machine to recognise it and POST, and then of course you can modify the timings in the bios so it will run at whatever.

or you just got lucky.
 
I just look at the manufacturer spec..... This is the first time I use DDR2 and Ive never had rams higher than PC5400 so I didnt even know about that JEDEC and SPD setting..... Im a lil behind with computer stuff cos its my first upgrade in 2 or 3 years......

Back to my rams, one set has D9's and the other ??? ( kingston cheappies..), guess I got lucky..... Excuse my n00bness in this topic but I still dont get why the lower rated rams cant be set higher if its capable of running at that speed? ( 533 running 667 5-5-5- in your example).... I know using 4 sticks, you are limited to how high your least performing ram goes, this I dont quite get......
 
no worries, I forget sometimes I been doing this stuff for probally too long :eek:



During the very first stages of the computer starting up, the processor/memory controller has to have some basic information in order activate the memory and get it working, at some speed, any speed, remember the computer is really really stupid at this stage. Also the engineers at Intel decided they would try an accomodate mismatched memory timings. The computer cant read ram labels, it has to get information from somewhere (it is not yet even smart enough to read your bios settings yet) and a bunch of stuff is programmed in the SPD chip, the physical layout of the rows and colums for memory addressing and data storage, just tons of low level technical information is stored in the SPD chip so the computer/MCH can then understand how to read and write to the memory and get it up and running in a basic way. Well then here comes the problem with mismatched sticks, suspose one slow stick and one fast stick, you cant speed up the slow stick (or if you could how would you know it would work with any slow stick ? ) , but the computer does not know that, yet. So the engineers had to come up with a scheme to handle that issue, ok, easy, slow down the fast stick. but to what ? They could assume the fast stick will run like the slow stick, but engineers HATE assuming things, cause when it does not work the airhead marketing jocks with all the women and fancy cars and no outsourcing worries come down to the lab and chew em out. (Bitter?, you bet!) So now, the computer need to make sure (becase sticks on the same channel, well both channels really, ALL have to run at the same speed and timings. they all share the same buss.) of some setting they all will work at. So they decided that all memory sticks MUST share a common set of standard timings programmed in the SPD chip, that way they can be postive of it all working, or not working. Engineers also hate stuff that only works some of the time, it is impossbile to deal with in an effecient manner. So basically I think thats why it is like it is. All modern memory has the SPD chip, the JEDEC standards are, well, standards and it gave them a lowest common denominatior they could rely on. I will not get into the nasty habit of a lot of memory manuf being very very lazy about properly populating the SPD chip with all necessary info.

Hope that helps some, its simplified and its just the way I understand it in a simplifed manner, there are probally some mistakes but I think it conveys the general idea.

Of course once the computer gets the memory up and running, activates the card slots, looks for disk drives etc etc. somewhere in that start up process it looks at your bios settings and goes Ah HA ! and sets the memory controller to run with what you put in.
 
Got it... thanks for the explanation....

So that problem I had with my ballistix not able to boot at 1.8v, who do I blame, my rams or my chipset? Im thinking more the rams thats why theyre in RMA right now.... Thats the only reason I got these cheap rams to begin with....could have got D9's for about the same price but Im thinking I might need these just in case.....
 
Got it... thanks for the explanation....

So that problem I had with my ballistix not able to boot at 1.8v, who do I blame, my rams or my chipset? Im thinking more the rams thats why theyre in RMA right now.... Thats the only reason I got these cheap rams to begin with....could have got D9's for about the same price but Im thinking I might need these just in case.....

oh man, that is a good question, wow the trouble we had when the P965s all came out, Hard to say, the Intel requirement for 1.8V and the JEDEC standard had been out there for a long long time. Plenty of blame on both sides.

If I had to blame someone, being trained as an engineer, I would put most of it on the memory manufacturers that sell memory that REQUIRES more voltage than standard to even work. yes it overclocks like mad or whatever once you give it the juice etc. etc. but its like being sold a very expensive high performance engine for your car and then finding out it will not fit under the hood.

we deserve some blame too, the issue was discovered almost on day one of the P965 boards being released back in sept of last year. However with all the marketing BS and the use of marketing crap in place of true electrical specifications, its a very very small part of the blame
 
I dont regret getting my board at all, it was my only option at the time cos the striker is too much money and I believe in Intel=Asus w Intel chipset AMD=DFI w Nvidia chipset...... kinda like you cant go wrong in buying a Sony TV.......
 
How about 3 stick, if they have the same same JEDEC timings, Will it work?

I have 3 stick, 2 of them are the identical, and another one is not.
If I send the different one to RMA, will they reprogram the spd? It is a gskill 1gb ddr2 800
 
How about 3 stick, if they have the same same JEDEC timings, Will it work?

I have 3 stick, 2 of them are the identical, and another one is not.
If I send the different one to RMA, will they reprogram the spd? It is a gskill 1gb ddr2 800

Well all I can say is that it is susposed too. And it wont hurt to try, it just wont POST power on self test and give you the magic "one beep".

Have to ask Gskill about the rest of it.
 
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