TSMC Claims 5nm Production is on Track

AlphaAtlas

AlphaAtlas

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Last year, Taiwan Semiconductor, who is responsible for manufacturing all of AMD's recently announced 7nm products and will presumably make Nvidia's 7nm GPUs, said that they'll start 5nm production with full EUV in April 2019 last year. But making chips at bleeding edge nodes is a hard business, to say the least. Delays tend to arise when production problems rear their ugly heads, and bad economics can make transitions to a new node cost prohibitive. But fortunately, at their conference call this year, TSMC said that that their 5nm process is still on track for 1H 2019, and that they're already engaging with HPC and smartphone customers. With the recent decline in smartphone sales, and ever-changing trade tensions with China, TSMC stock has fallen significantly these past few months, and naturally, investors asked a lot of pointed questions. But TSMC seems confident that companies will aggressively adopt their 5nm and 7nm process anyway due to the significant performance advantages they will offer over older nodes. Mark Liu also mention that "almost all" of TSMC's customers want to adopt their relatively new advanced packaging services, meaning that multi-chip products like HBM GPUs or CPUs with an I/O die might be a more common sight on the 5nm node. He also mentioned that cryptocurrency mining had a significant impact on their business, one they didn't see coming last year. Thanks to Digitimes for spotting the conference call, even though they didn't link it.

Even with a slow year like 2019, we firmly believe AI and 5G are the megatrends that will drive the future semiconductor growth. And were affirm our long-term growth projection of 5% to 10% CAGR. Now I will talk about our 5-nanometer status. Our N5 technology development is well on track, with customer tapeout schedule for first half 2019 and volume production ramp in first half 2020. We are already in preparation for N5's ramp. All applications that are using7-nanometer today will adopt 5-nanometer. In addition, we are expecting the customer product portfolio at N5 and see expanding addressable market opportunities. We expect more applications in HPC to adopt N5. Thus we are confident that N5 will also be a large and long-lasting node for TSMC... 5-nanometer are ramping in 2020. I would expect that product portfolio is expanding more as compared with the 7-nanometer in 2018.
 
5nm Radon Vega VIII inbound for 2020..... Joking aside I wonder if Nvidia will jump to 7nm or 5nm? Wonder what the power and performance difference between the two will be.
 
Intel - we've got 10nm
TSMC - Hold my beer.

But on topic: Radeon Navi 2020 should be a headturner if they can go to 5nm but I think their last roadmap said 2020 Navi was 7nm still.
 
Wanted to add:

1-AMD-CES-GPU-Feature-.jpg


7nm Plus so I guess it could mean 5 right?
 
dvsman said:
Pretty Cool! But how low can we go ... ?
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I wonder the same. What node size is generally considered to be the theoretical minimum at any cost, and which process size is considered to be the practical minimum for consumer products without driving the cost too high?


Someone has to have written something about this, but googling it, it is surprisingly sparse.
 
Nodes 3nm and 2nm are in development per EETimes.
 
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Zarathustra[H] said:
I wonder the same. What node size is generally considered to be the theoretical minimum at any cost, and which process size is considered to be the practical minimum for consumer products without driving the cost too high?


Someone has to have written something about this, but googling it, it is surprisingly sparse.
Click to expand...

This is a good article to read for some answers to your question.

EUV Lithography Finally Ready for Chip Manufacturing

So there is already a pathway to 1 nm processing, but with serious complications that still need to be overcome (and it's absolutely not cost-effective).
 
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Honestly, you could probably get just below 1 nm in some highly specialized research experiments. However, once you get down to issues with the actual spacing between atoms, you just can't get around quantum tunneling effects. There was that research group out of Europe a year or two ago that made a transistor with 3 atoms. You don't see this being rolled out in large-scale production.
 
Zarathustra[H] said:
I wonder the same. What node size is generally considered to be the theoretical minimum at any cost, and which process size is considered to be the practical minimum for consumer products without driving the cost too high?


Someone has to have written something about this, but googling it, it is surprisingly sparse.
Click to expand...

I recall reading that 3nm was the point where things start to get really muddy.
 
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