Toshiba Libretto 50ct teardown and possible project

cdabc123

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Had this laptop sitting around and after diving in the construction and design really interested me.

Currently have no idea if it even powers on. Adapter is on the way. After that I get to dive into the majical world of win 95 to try and get a os crawling on this thing.

As far as projects go this has a very well documented io sheild. Since this is already a external device I want to intigrate a tiny fpga with it to deal with any io weirdness I want to use this thing for. Im also looking to integrate a rpi nano and remote into it and use that for modern internet access.

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serpretetsky

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Lattice Semiconductor MachXO3 FPGAs are pretty good for small low-cost FPGAs. FPGA flash configuration and oscillator on the chip, all you need to do is supply 3.3V (and any related bypass capacitors) and you're good to go. I do recommend bringing out the jtag pins as well for easy debugging and programming. The tools work on modern machines too (I was using Diamond Lattice with windows 10).
 

cdabc123

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Lattice Semiconductor MachXO3 FPGAs are pretty good for small low-cost FPGAs. FPGA flash configuration and oscillator on the chip, all you need to do is supply 3.3V (and any related bypass capacitors) and you're good to go. I do recommend bringing out the jtag pins as well for easy debugging and programming. The tools work on modern machines too (I was using Diamond Lattice with windows 10).
I was looking at diving into the lattice devices as some of the offering fit the form factor perfectly. I need to get a better idea of what I expect out of the fpga. I do have regulated power as well as serial and various other io from the laptop.

I was also leaning to a larger xilinx or altera fpga as I have a reasonable x y space to work with if I minimize the z space. I'm also already familiar with quartus and vivado.

Lol, what debug and programming options work on win 95? :p
 

serpretetsky

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win95? I haven't checked but for Xilinx it would probably be ISE. I believe that supports most xilinx FPGA's/CPLD's before the 7 series (and some 7 series?). I think i was more assuming you would synthesize and/or program from a different machine and then generally keep that fpga image semi-permanently until you needed to change it for some reason. But i dont know how you envision your use-case.

Synthesis on that machine will be pretty slow, but for smaller FPGAs maybe it will be fine?

Im not familiar with Altera.
 

cdabc123

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win95? I haven't checked but for Xilinx it would probably be ISE. I believe that supports most xilinx FPGA's/CPLD's before the 7 series (and some 7 series?). I think i was more assuming you would synthesize and/or program from a different machine and then generally keep that fpga image semi-permanently until you needed to change it for some reason. But i dont know how you envision your use-case.

Synthesis on that machine will be pretty slow, but for smaller FPGAs maybe it will be fine?

Im not familiar with Altera.
Lol I definitely will build the fpga on a different device. I'm just curious what the fpga scene looked like for win 98 ish.

Is the lattice toolchain pretty decent to build from?
 

serpretetsky

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Is the lattice toolchain pretty decent to build from?
It was good enough for me. Lattice Diamond tools. My designs were generally pretty small and typically didn't push clock timing very hard. Generally I dont use the IDE for writing HDL, prefer notepad++ or visual studio code. The free version currently comes with modelsim for simulation, which is ok (I remember preferring activeHDL which they recently switched away from, just generally more responsive and more stable). For verilog it supports many verilog/systemverilog 2009 constructs. I'm not sure how good the VHDL 2008 support is.

I never got the reveal logic analyzer to work ( equivalent to Xilinx ILA). So there's that.

If you want to instantiate a soft cpu they have the Lattice Mico 32 (LM32) and Lattice Mico Development tools (c compiler) which integrates with Lattice Diamond tools. You can recompile code and not resynthesize anything, just reinitialize the BRAM. I've heard they're moving away from the LM32 and moving towards RISCV so maybe there are other options there (Lattice Propel i think?).

They generally support wishbone bus for LM32 and MACHXO3 / MACHXO2 fpgas, but maybe with RISCV they've moved to AXI, not sure.
 
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