During the International Solid State Circuits Conference (ISSCC) in San Francisco, SK Hynix chip designer Dongkyun Kim presented a paper on the company's first Double Data Rate 5 (DDR5) chip that features 16Gb 6.4Gb/s/pin SDRAM that runs at 1.1V and measures 76.22mm2. SK Hynix uses a 1ynm, 4-metal DRAM process to manufacture the chips. Dylan McGrath of EE|Times noted that the DDR5 spec hasn't been finalized but is expected to offer "double the bandwidth and double the density of DDR4 along with delivering improved channel efficiency." Samsung was much more secretive with their 10nm-class LPDDR5 SDRAM capable of up to 7.5Gb/s at 1.05V. The JEDEC LPDDR5 standard will "operate at an I/O rate of 6400 MT/s, 50% higher than that of the first version of LPDDR4" and will "boost memory speed and efficiency for applications including smartphones, tablets and ultra-thin notebooks." DDR5 -- or Double Data Rate 5 -- is still under development at the Jedec standards organization. DDR5 offers double the bandwidth and double the density of DDR4 along with delivering improved channel efficiency. The standard was expected to be finalized last year, but remains a work in progress. DDR5 products are now expected to appear beginning late this year.