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erek
[H]F Junkie
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- Dec 19, 2005
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More exciting RISC-V news
“Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.
Uniquely, Semidynamics offers a second key choice in the Vector Unit: the number of bits of each vector register (known as VLEN) can also be tailored to customer’s needs. While most other vendors assume that VLEN is equal to DLEN (i.e., 1X ratio), Semidynamics offers 2X, 4X and 8X ratios. When the VLEN is larger than the DLEN, a vector operation uses multiple cycles to execute. For example, when VLEN=2048 and DLEN=512, each vector arithmetic operation will take 4 clocks to execute. This is a great feature for tolerating large memory latencies and for reducing power.
“This unleashes the ability for the Vector Unit to process unprecedented amounts of data bits,” added Espasa. “And to fetch all this data from memory, we have our Gazzillion™ technology that can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Together our technologies take RISC-V to a whole new level with the fastest handling of big data currently available that will open up opportunities in many application areas of High-Performance Computing such as video processing, AI and ML.”
The new Vector Unit is Out-Of-Order and pairs with Semidynamics’ Out-Of-Order Atrevido core and upcoming In-Order cores. If required, Semidynamics can do Open Core Surgery™ on cores and Vector Units to provide special interfaces and protocols to a customer’s proprietary IP block.”
Source: https://www.eejournal.com/industry_...on-per-cycle-for-unprecedented-data-handling/
“Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.
Uniquely, Semidynamics offers a second key choice in the Vector Unit: the number of bits of each vector register (known as VLEN) can also be tailored to customer’s needs. While most other vendors assume that VLEN is equal to DLEN (i.e., 1X ratio), Semidynamics offers 2X, 4X and 8X ratios. When the VLEN is larger than the DLEN, a vector operation uses multiple cycles to execute. For example, when VLEN=2048 and DLEN=512, each vector arithmetic operation will take 4 clocks to execute. This is a great feature for tolerating large memory latencies and for reducing power.
“This unleashes the ability for the Vector Unit to process unprecedented amounts of data bits,” added Espasa. “And to fetch all this data from memory, we have our Gazzillion™ technology that can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Together our technologies take RISC-V to a whole new level with the fastest handling of big data currently available that will open up opportunities in many application areas of High-Performance Computing such as video processing, AI and ML.”
The new Vector Unit is Out-Of-Order and pairs with Semidynamics’ Out-Of-Order Atrevido core and upcoming In-Order cores. If required, Semidynamics can do Open Core Surgery™ on cores and Vector Units to provide special interfaces and protocols to a customer’s proprietary IP block.”
Source: https://www.eejournal.com/industry_...on-per-cycle-for-unprecedented-data-handling/
