Overclocker pushes a 14-year-old Celeron to 8.36GHz

That is very high. But, some games don't care about higher clock speeds and more about cores / threads. It would give a boost in performance but, not that much in some game titles. Also good luck cooling it!
 
Hematite said:
That is very high. But, some games don't care about higher clock speeds and more about cores / threads. It would give a boost in performance but, not that much in some game titles. Also good luck cooling it!
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Lol I think you missed the entire point here. That chip is built on Netburst architecture. It would suck even at 20Ghz.
 
FlawleZ said:
Lol I think you missed the entire point here. That chip is built on Netburst architecture. It would suck even at 20Ghz.
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Yeah, I think using that Celeron for the record is the high clock -to-fsb ratio; you can push the thing to 7.5 Ghz before you even leave the OFFICIAL Intel defined 1333 FSB speeds!

They also come with no complexity like hyperthreading, plus the smallest cache you can buy in a modern process node. And later P45 motherboards can hit 1800 mhz FSB (so you just have to provide nitro cooling plus the golden chip!)

Going to be dog-slow.
 
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I wonder at that frequency how close we get for the longest signal route it is possible to occur in the CPU pathways to have light speed becoming a limitation.

I think during 1/8.36g of a second, information or light cannot effectively travel more than 3.6 centimeter, which it is a bit crazy to think of, that this I imagine could start to be something to think about inside a chip (and not for satellite signal or long distance networking).
 
LukeTbk said:
I wonder at that frequency how close we get for the longest signal route it is possible to occur in the CPU pathways to have light speed becoming a limitation.

I think during 1/8.36g of a second, information or light cannot effectively travel more than 3.6 centimeter, which it is a bit crazy to think of, that this I imagine could start to be something to think about inside a chip (and not for satellite signal or long distance networking).
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oh no, the die size of Cedar Mills is81 mm^2 assuming roughly square, say 8 x 10 mm. that's well-under 3.6 centimeter.

Like;y the limiting factor at thpse speeds is interconnect resistance.
 
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defaultluser said:
oh yes, the die size of Cedar Mills is81 mm^2 assuming roughly square, say 8 x 10 mm. that's well-under 3.6 centimeter.

Like;y the limiting factor at thpse speeds is interconnect resistance.
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I would imagine that some signal total possible datapath are far from a straight line and considering that 3.6 centimeter that exactly the outside of such sized square, i.e. light that would simply circle around that chip using the smaller possible circle would take more time that the length of a clock cycle of that cpu, we are talking at least to be in similar scale of measure. And that using speed of light going on in empty space, I imagine signal/electricity in silicone is a bit slower than that.

Maybe I am mistaken, but 0.8 cm + 1 cm + 0.8cm + 1 cm to circulate a signal of the edge of that square, that a 3.6 cm line, .8 cm by 1 cm isn't that well under 3.6 cm

When we look to a cpu datapath there is a some turn and none straight line:


I could imagine that when you go to the 10-20 ghz not only gates, transistor shift and all other timed operation are a variable but actual information travel time on a trace even at near perfect speed of light can become part of the equation of your longest possible critical data path that will limit your maximum frequency. At 20 ghz you would already go at less than 1.5 cm, that would be really close to the diagonal of a 8x10mm chips (1.28cm)
 
LukeTbk said:
I would imagine that some signal total possible datapath are far from a straight line and considering that 3.6 centimeter that exactly the outside of such sized square, i.e. light that would simply circle around that chip using the smaller possible circle would take more time that the length of a clock cycle of that cpu, we are talking at least to be in similar scale of measure. And that using speed of light going on in empty space, I imagine signal/electricity in silicone is a bit slower than that.

Maybe I am mistaken, but 0.8 cm + 1 cm + 0.8cm + 1 cm to circulate a signal of the edge of that square, that a 3.6 cm line, .8 cm by 1 cm isn't that well under 3.6 cm

When we look to a cpu datapath there is a some turn and none straight line:


I could imagine that when you go to the 10-20 ghz not only gates, transistor shift and all other timed operation are a variable but actual information travel time on a trace even at near perfect speed of light can become part of the equation of your longest possible critical data path that will limit your maximum frequency. At 20 ghz you would already go at less than 1.5 cm, that would be really close to the diagonal of a 8x10mm chips (1.28cm)
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A chip designed to clock as high as the P4 has nearly 30 pipeline stages in order to make each buffered stage happens as quickly-as-possible This include speed-optimization (ike the double-speed ALU!)

https://www.realworldtech.com/forum/?threadid=2538&curpostid=2544

I guarantee you that in any properly-designed Intel processor (using optimized libraries and automated-layout), the longest-possible critical path is going to be the length of the chip Even going corer to corner, that is still less than 14 mm

Is it getting close? sure. but at 8ghz, on those smaller process nodes, the biggest limiting factor is going to be RC interconnect delay ( way higher on those tall interconnect)
 
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Pretty cool a kid did it, props to him. 8GHz P4 was done like 13 years ago or more, so not really news that it can be done. Pretty neat that someone born at the time it was done is now doing it himself though.
 
defaultluser said:
I guarantee you that in any properly-designed Intel processor (using optimized libraries and automated-layout), the longest-possible critical path is going to be the length of the chip Even going corer to corner, that is still less than 14 mm

Is it getting close? sure. but at 8ghz, on those smaller process nodes, the biggest limiting factor is going to be RC interconnect delay ( way higher on those tall interconnect)
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I feel like you are speaking as if 14 mm is in a different realm than the 36 mm light can travel during that clock circle and say 34 mm information via electricity tension do at high temperature in those path. It is not like I am comparing 10 of mm with meter, I am comparing tens of mm with tens of mm.

The biggest limiting factor must be something else, my original point if it was not clear, it is crazy to think that it would start to be one factor, that like ok all the relay/gate/transistor shift take 0.05 nano second, actual information transfer in the equivalent of cable is 0.01 nano second thus costing 15% on the maximum theoric frequency the CPU can reach in a perfect circuitery.
 
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