Pyrolistical
Gawd
- Joined
- Mar 6, 2003
- Messages
- 737
The OCZ Colossus will put 4 Indilinx controllers in a single 3.5" enclosure. If the colossus is more than 4x the performance of a vertex, then with a queue depth of 4 the colossus 4k random read is 64*4 = 256 MB/s, or in other words it is SATA II bottle necked!!!
That's insane! There's little point in even looking at seq read/write if the random read is already bottle necked.
Also, SATA 6 Gbps will be obsolete by the time it comes out. Considering a single Vertex already maxes out the seq read, a colossus would need more than 24 Gbps.
And this is extrapolating using existing technology. I think we have plenty of room for improvement. A single barefoot controller only uses 4 channels, and a vertex has 16 flash chips! This means if the future gen barefoot have 16 channels, that's a 4x improvement. (Intel's controller is already at 10 channels. But also note that Intel fit 20 chips in their 2.5" enclosures, so it makes sense if there were a 20 channel controller in the future)
So next gen SATA would have to be at least 4*24 Gbps = 96 Gbps if it wants to exceed the capabilities of SSDs. (That is assuming you toss in 4 of these controllers in a 3.5" enclosure. You could definitely make custom chips that have more than 64 channels, but it makes more sense to use the same controller for 2.5" and 3.5" drives)
This far exceeds the 10 Gbps limitation of the DMI between the north and south bridge in a x58. Which means the next next gen SATA controller needs to be moved to the north bridge, or even moved directly on-board the CPU like the memory controller was. Sweet, sweet latency reduction!
And I am only talking about ONFI 1.0. Next gen ONFI nand flash is even faster per channel!
That's insane! There's little point in even looking at seq read/write if the random read is already bottle necked.
Also, SATA 6 Gbps will be obsolete by the time it comes out. Considering a single Vertex already maxes out the seq read, a colossus would need more than 24 Gbps.
And this is extrapolating using existing technology. I think we have plenty of room for improvement. A single barefoot controller only uses 4 channels, and a vertex has 16 flash chips! This means if the future gen barefoot have 16 channels, that's a 4x improvement. (Intel's controller is already at 10 channels. But also note that Intel fit 20 chips in their 2.5" enclosures, so it makes sense if there were a 20 channel controller in the future)
So next gen SATA would have to be at least 4*24 Gbps = 96 Gbps if it wants to exceed the capabilities of SSDs. (That is assuming you toss in 4 of these controllers in a 3.5" enclosure. You could definitely make custom chips that have more than 64 channels, but it makes more sense to use the same controller for 2.5" and 3.5" drives)
This far exceeds the 10 Gbps limitation of the DMI between the north and south bridge in a x58. Which means the next next gen SATA controller needs to be moved to the north bridge, or even moved directly on-board the CPU like the memory controller was. Sweet, sweet latency reduction!
And I am only talking about ONFI 1.0. Next gen ONFI nand flash is even faster per channel!
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