Q2/Q3 for 7nm server and latter for 7nm desktop is the repeated rumor.
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New Zen 2 Leak
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Q2/Q3 for 7nm server and latter for 7nm desktop is the repeated rumor.
Just joined to read something about a new leak. Only found Jim inventing stuff.
I just clicked the link in your signature
Code:
mov ecx, 10
mov edx, 3
add eax, ecx
add ebx, edxOnly to realize you know nothing of x86 compilers.
Code:
mov eax, dword ptr [a]
add eax, 10
mov dword ptr [a], eax
mov ebx, dword ptr [m]
add ebx, 3
mov dword ptr [b], ebx
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Did they announce vega and give a date until it was actually launched? So I meant what I said. They announced the CPUs and said when they will be available. They didn't do that with Vega, they actually never announced vega until it was late as well.
Did you really not understand what I typed? I said They never let down on CPU launches. They announced and gave a date and delivered. Hell I agreed about vega. Not sure where the disconnect is from what I said lol.
Are you actually saying they were late on luanching CPUs when it came to zen and zen+ and they were late? No they weren't! They announced and gave availability date how the hell is that late? They can easily do the same if they think they can deliver them by Lat march or early April.
sirmonkey1985
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hopefully with the old gpu marketing team gone the shit fest that was Vega launch won't happen again. 9 months of hyping up a product with no release date til it just randomly launched out of no where similar to what they tried to do with bulldozer.
IdiotInCharge
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Lot of speculation here: Intel and AMD do quite a bit of massaging of their architectures to fit their processes, and do quite a bit of efficiency work on top of that too. AMD is certainly capable of doing the same, but it's work that must be done well for them to compete.
There is not much speculation here. It's a fact that AMD tops out at 4.2Ghz currently.
Its a safe bet that AMD will reach approximately 5Ghz on TSMC Zen 2.
It's also a fact that Intel is currently operating at 5Ghz.
I will agree that GPU clock is speculation, but the rest is more likely than not.
IdiotInCharge
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Boost speeds? Maybe. All core? Not really a safe bet, and that's where Intel's at on a larger process
I would not consider Intel 14nm ++++ to be larger than TSMC "7nm"Boost speeds? Maybe. All core? Not really a safe bet, and that's where Intel's at on a larger process
I consider them to be roughly equal, and once Intel irons out 10nm in 2020 it will likely pull ahead of TSMC 7nm
If intel is having such a hard time to launch 10nm then i highly doubt that on the first go they would be better than 7nm out the game. Intel really has been tweaking 14nm for years. THis is the first go at 7nm. So I expect 7nm iterations to get better as the time goes on as well. And then 5nm. But I go expect 7nm node to mature much better as time goes on.
luminousone
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https://github.com/gnif/LookingGlass
Your absolutely right, Not that hard to think of things that can beat PCIE 3.0 up.
Never Enough!
Lol. Looks like someone has comprehension issues. I am not 15. Not sure why you are so confused.
AMD - Ryzen will be available at this date. And it was.
Vega - was a shit show and we a knew it was late .
Now why are you so confused? Why is it so hard for you to believe they could announce the lineup in January and give an availability date for March or April?
dgz
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Ain't no such thing as safe bet, mon. Don't get people's hopes up.
IdiotInCharge
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TSMC seems to be pretty solid for Nvidia. I'm thinking it will be a good improvement over Global Foundries.
TSMC has been fairly good for nvidia GPUs. I think they are pretty dang good at this point. Samsung is good but their 7nm is yet to be seen. I am sure they will do pretty good as their Foundry business is extremely important to them and brings in alot of profits too.
IdiotInCharge
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Sure, but we're talking about 5GHz small dies, not 2GHz large ones here.
It's a different thing, as well as TSMC has worked out for Nvidia.
sirmonkey1985
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I'd put my money on tsmc.
So you're saying TSMC has a custom node just for nVidia?
I find that economically farcical, please back this up.
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IdiotInCharge
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Should find it highly likely that both Nvidia and TSMC have been making adjustments based on what the processes and designs are capable of. Nvidia is a high-profile customer for TSMC.
In a nutshell, AMD or someone released a smoke bomb. Why not put doubt in those getting ready to purchase parts for Intel or Nvidia?
The problem I have with a 16 core Ryzen, X570 based at 5ghz is that it would be memory starved with dual channel DDR4. Great at some things and very restricted in others. Really makes no sense and the power requirements, especially pushing clock speeds would be much higher then indicated on the Adored TV charts. Still talking about a design where a lot of it is 14nm. Now AMD can be kinda unclear when they deal with power ratings, as in Vega the power rating is based off of the GPU and not the whole board (HBM, VRM losses etc.). So 105w of power per chiplet???? Who knows.
Now I would be more than happy if AMD found and made work some evolutionary advancements - more fun times indeed! A low power 5ghz 8 core Ryzen would be awesome in itself, 12 cores??? 16 cores??? I just don't see TSMC capacity at 7nm being able to support all of this.
drescherjm
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I assume > 8C means 2 chiplets.
TSMC probably has plenty of capacity with apple cutting millions of orders for iPhones. So I am fairly confident AMD will be fine. Its not just capacity I think with chiplet design amd will have pretty damn epyc yields. I am not sure about the chip being memory starved lets see what kind of improvements they have made with the IO die.
DuronBurgerMan
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I suspect folks are right that the supposed 16 core will be a bit bandwidth starved in some situations. Even with faster RAM and more cache, two channels will have to feed double the core count of today. Thus 16 core TRs will still have their place, by giving you quad channel and more consistent performance. However, a 12 core AM4 CPU may just be a sweet spot in terms of price, tdp, and memory utilization.
Assuming any of these rumors are true, of course.
Assuming any of these rumors are true, of course.
N4CR
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Yeah I don't see anything but memory segmentation between Server, HEDT, Desktop in future.
AMD has ECC on all platforms. Only current difference is no OC on servers and memory channels really.
luminousone
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Seems like a good thing to me, no games around instruction sets, or feature enablements(nvme raid, memory encryption(well partly), ecc, etc), pick yer core count, pcie lane count, and memory channel count. Makes it simple to pick the correct product for what you intend to run.
Not sure what magic AMD will do with basically the same memory bandwidth but double the cores, plus higher IPC in combination with higher core clocks. Sounds like that would be a very unbalanced design. Actually ThreadRipper 32 core with quad channel is very similar to come to think about it. So yes possible just seems odd and at times unbalance if the case. Maybe another high bandwidth cache controller option here?
Not sure what magic AMD will do with basically the same memory bandwidth but double the cores, plus higher IPC in combination with higher core clocks. Sounds like that would be a very unbalanced design. Actually ThreadRipper 32 core with quad channel is very similar to come to think about it. So yes possible just seems odd and at times unbalance if the case. Maybe another high bandwidth cache controller option here?
who knows. All I Know is that IO die is fuckin huge, so it must be magical lol!
luminousone
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Not sure what magic AMD will do with basically the same memory bandwidth but double the cores, plus higher IPC in combination with higher core clocks. Sounds like that would be a very unbalanced design. Actually ThreadRipper 32 core with quad channel is very similar to come to think about it. So yes possible just seems odd and at times unbalance if the case. Maybe another high bandwidth cache controller option here?
Actually, the new IO chiplet design should help memory bandwidth, All the memory channels are connected to it, instead of 8core monolithic dies, putting all memory on a socket at the same distance from all cores in the socket. The 32core threadripper chips have numa domains without any memory, causing all memory accesses to hit the coherency fabric.
The IO chiplet design could easily solve this, not with a full l4 cache, but just having a cache directory cache on the io die, this might be why the IO die is so large as well. Coherent memory accesses would no longer need to broadcast to all the core complexes, a simple lookup to the cache directory and a memory fetch would be enough. This design should heavily reduce coherency traffic, and given that the infinity fabric links have been doubled in speed to a 100gb as well, should make for an fast memory system.
I would further note that given what I have seen memory benchmark wise for epyc chips, and granted this won't apply to how the IO dies work, just having every numa domain populated with memory is the biggest difference maker.
https://www.servethehome.com/amd-epyc-naples-memory-population-performance-impact-at-16-cores/
note that going from 4 populated channels to 8 channels makes little difference in many benchmarks.
I await with great anticipation what these new monster chips are gunna do.
As everyone except you knows, Volta uses a custom 12FFN process (FinFet Nvidia). So, even ignoring microarchitecture differences, you cannot take Nvidia clocks as reference for estimating clocks of standard process nodes used by AMD.
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Having the memory controllers in a central IO doesn't change the memory bandwidth. If Rome is eight 3200-DDR4, then the peak bandwidth will be 205 GB/s (up from 171 GB/s); that is only a 20% improvement for 2x/4x higher peak throughput. The extra L3 will help, but cache cannot fake memory bandwidth. Rome will have worse GB/IOP and GB/FLOP ratios than Naples.
luminousone
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The link I provided clearly shows the epyc chips are not bandwidth starved or even close to it. Going from 4 channels to 8 channels does not make a large difference in performance in most benchmarks. I also pointed out multiple mechanisms that would help with the issue otherwise. And I didn't even point to the doubled l3 cache.
KazeoHin
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The issue with Ryzen memory sensitivity is its wierd reliance on memory clockspeed for IF speed. It has nothing to do with bandwidth. I can't think of ONE application that is memory-bandwidth bottlenecked on the Ryzen processors. Increasing the core count doesn't mean the CPU needs more bandwidth inherently, it means that it's performance increases overall, and if bandwidth is identical, certain tasks are MORE LIKELY to run into a bandwidth limitation. There is nothing saying all 16 cores will be inherently slowed down by dual- channel memory.
No.
(i)
"Going from 4 channels to 8 channels" for 16C EPYC is going from 4 cores per channel to 2 cores per channel. So it is like going from non-existent 16 channel 64C Rome to a non-existent 32 channel 64C Rome. Or like going from non-existent 16C AM4 Ryzen with 4 channels to a non-existent 16C AM4 Ryzen with 8 channels. That is not what will be happening with Zen2.
64C Rome has only 8 channels and AM4 has only 2 channels. So the relevant measurements in the review are those with 16C EPYC going from 4 channels to 1 channels for floating point benchmarks and those going from 4 channels to 2 channels for integer benchmarks because Zen2 has ~2x GB/IOP and ~4x GB/FLOP lower ratios than Zen.
That review is testing 16C EPYC with full 64 MB cache. So it is already considering the effect of the large L3 on Zen2 (4MB per core).
(ii)
STH tests some joy-benches like their C-Ray workload, which fits into cache. Real-life memory-bound workloads (e.g. many HPC workloads) will behave as in the STREAM benchmark.
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