Micron Delivers the Industry's First 1α DRAM Technology

[erek]

""Our new 1α DRAM technology will enable the industry's lowest-power mobile DRAM as well as bring the benefits of our DRAM portfolio to data center, client, consumer, industrial and automotive customers," said Sumit Sadana, executive vice president and chief business officer at Micron. "With our industry leadership in both DRAM and NAND technology, Micron is in an excellent position to leverage the growth in memory and storage, which are expected to be the fastest growing segments in the semiconductor industry over the next decade."

Micron's 1α DRAM node will facilitate more power-efficient, reliable memory solutions and provide faster LPDDR5 operating speeds for mobile platforms that require best-in-class LPDRAM performance. Micron's innovation brings the industry's lowest-power mobile DRAM, with a 15% improvement in power savings,1 allowing 5G mobile users to perform more tasks on their smartphones without sacrificing battery life.

Micron's advanced memory node supports densities from 8Gb to 16Gb, offering the flexibility to sustain many of Micron's current DDR4 and LPDDR4 products while giving Micron's server, client, networking and embedded customers the power-efficient, reliable, extended product support they need. This longevity reduces the cost of customer requalification within their own product lifecycles. It also ensures better total cost of ownership over the system life in use case scenarios such as embedded automotive solutions, industrial PCs and edge servers that typically have longer lifespans.

Availability
Micron's Taiwan fabs have begun volume production of 1α node DRAM, starting with DDR4 memory for compute customers and Crucial consumer PC DRAM products. Micron has also begun sampling LPDDR4 to mobile customers for qualification. The company will introduce additional new products based on this technology throughout calendar 2021."

https://www.techpowerup.com/277733/micron-delivers-the-industrys-first-1-dram-technology

 

[Armenius]

Going to need an explanation of the 1α node, not some marketing speak.

 

[1_rick]

Going to need an explanation of the 1α node, not some marketing speak.

Weren't they doing "1x, 1y, 1z" as a way of avoiding specifying where those nodes were in the 10..19 range? After 1z, you go to the Greek alphabet. Maybe it's the equivalent of 14+++.

 

[Armenius]

Weren't they doing "1x, 1y, 1z" as a way of avoiding specifying where those nodes were in the 10..19 range? After 1z, you go to the Greek alphabet. Maybe it's the equivalent of 14+++.

I found something that said the words are a lot tighter on this process, which would explain the efficiency bump. Nothing anymore technical than that I can find. Micron is really tight lipped about their stuff.

 

[1_rick]

I found something that said the words are a lot tighter on this process

I was being flippant, but I was also kinda being serious.

 

[Armenius]

I was being flippant, but I was also kinda being serious.

I see that in the last sentence, but the first part is true from what I've read since posing the initial question.

 

[defaultluser]

Going to need an explanation of the 1α node, not some marketing speak.

Memory can't scale beyond 10nm, so they have use hacks, and they just rename the process tick.

If you're wondering why you only saw a quadrupling in memory density over the last six years, that is the reason.

https://semiengineering.com/dram-scaling-challenges-grow/

Remember that, prior to us hitting the 300mm wafer size limit, half of Moore's Law's gains were from with increasing your fab's wafer size, or massive improvements in the chemistry / materials used in your fab. We've kind hit a wall on both of those, so we're left with completely redesigning the transistor layout to keep the optical shrinks working (takes forever, and the gains are not what hey used to be).