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Honestly, the way I see it is that these fancy new PCIe generations don't matter much.
Today, the only devices I have that even use Gen 3 are my GPU and NVMe drives. Everything else is Gen 1 or Gen 2.
So the way I see it is, when these standards first launch, they will be non-issues, until way down the line.
Honestly, the way I see it is that these fancy new PCIe generations don't matter much.
Today, the only devices I have that even use Gen 3 are my GPU and NVMe drives. Everything else is Gen 1 or Gen 2.
So the way I see it is, when these standards first launch, they will be non-issues, until way down the line.
They might not matter to the end points, but it does allow for more bandwidth between the CPU and chipset, which in turn allows the chipset to handle more end points. Of course getting the OEM to design things that way is another matter.
Agreed.
That is the biggest benefit for now.
I'm still disappointed AMD decided to keep only 4x lanes between the CPU and the x570 chipset. Sure that is double the bandwidth of their previous designs with Gen 3, but they also have the ability to use 40 lanes off of the chipset. That's a lot of lanes sharing that bandwidth.
Wonder if anyone visited all the intel code name places