Intel's answer to AMD's HyperTransport?

perplex

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I remember reading something about Intel's research on something similar to AMD's HyperTransport, called CSI? Does anyone have more information on this and/or know when Intel will be implementing it into their CPU designs? The next generation, Merom-based CPUs such as Conroe won't be using it we know for sure.
 

HighwayAssassins

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I havent heard anything of this sort...would be interesting to see what they come up with, if it is infact true.
 

pxc

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HighwayAssassins said:
Oh, but thats for Itanium...not for home users....
CSI for Xeons (2007) was announced at Spring IDF 2005. It was supposed to follow for desktops in 2008.

Yonah doesn't seem to be suffering too much, but the high end will.
 

perplex

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Yeah I heard the FSB bottlenecking becomes significant after and around 4 way systems. So what about quad and octa core Intel CPUs in 2008+ ? :confused:
 

Duke3d87

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perplex said:
Yeah I heard the FSB bottlenecking becomes significant after and around 4 way systems. So what about quad and octa core Intel CPUs in 2008+ ? :confused:
4P systems are already a problem so Intel is going to make multiple independant front side busses. But try feeding four 1333 MHz FSBs! BTW, the first quad core will be out in H1 of 2007
 

savantu

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Duke3d87 said:
4P systems are already a problem so Intel is going to make multiple independant front side busses. But try feeding four 1333 MHz FSBs! BTW, the first quad core will be out in H1 of 2006.

Well , that isn't really a problem.

Intel's 8500 chipset with DIB for Xeon MPs has an agregate memory BW of 21GBs read and 8.5GBs write to the main memory using the 4 external memory controllers.And this is one year old in a month or 2....
 

Duke3d87

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savantu said:
Well , that isn't really a problem.

Intel's 8500 chipset with DIB for Xeon MPs has an agregate memory BW of 21GBs read and 8.5GBs write to the main memory using the 4 external memory controllers.And this is one year old in a month or 2....
I see your point. But, when you go to dual core, you still have a big problem; four cores (two dual core processors) sharing a 667 MHz FSB. And with the 21 GB/sec, that's only like 5 GB/sec/processor and the P4 lives off bandwith. I think it will get better, but I would have liked for Intel to release a 1 GHz+ FSB XeonMP to make them a bit more competitive
 

perplex

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Duke3d87 said:
4P systems are already a problem so Intel is going to make multiple independant front side busses. But try feeding four 1333 MHz FSBs! BTW, the first quad core will be out in H1 of 2006.

Typo? you mean "H1 of 2007" ?
 

savantu

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Duke3d87 said:
I see your point. But, when you go to dual core, you still have a big problem; four cores (two dual core processors) sharing a 667 MHz FSB. And with the 21 GB/sec, that's only like 5 GB/sec/processor and the P4 lives off bandwith. I think it will get better, but I would have liked for Intel to release a 1 GHz+ FSB XeonMP to make them a bit more competitive

Tigerton will have 1 FSB/socket and I expect it to be 1333Mhz as Woodcrest hints...
4 sockets = 4 x1333 = 42 GBs to 8/16 cpus.That is truly a beast for a 4 socket machine.

As for the current Xeon MPs they are very competitive , in fact they beat any Opteron based server in most industry benchmarks.And they scale up to 32 sockets / 64 cores now.

IBM 366/460 are the most powerfull x86 based servers on the market.

But Opteron lives on thanks to the general hype...
 

Duke3d87

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savantu said:
Tigerton will have 1 FSB/socket and I expect it to be 1333Mhz as Woodcrest hints...
4 sockets = 4 x1333 = 42 GBs to 8/16 cpus.That is truly a beast for a 4 socket machine.

As for the current Xeon MPs they are very competitive , in fact they beat any Opteron based server in most industry benchmarks.And they scale up to 32 sockets / 64 cores now.

IBM 366/460 are the most powerfull x86 based servers on the market.

But Opteron lives on thanks to the general hype...

I think th e Tigerton will have faster then a 1333 Mhz FSB just because woodcrest will debut with a 1333 MHz FSB. See I didn't know that the MPs were compettive. From the benchmarks that i've seen, they aren't necessarly that good, but apparently, i was worng. And how is it that the Xeons beat the Opterons, in the MP (4P) but get beat in the DP? And how is it that the bandwith starved MP outperforms the Opteron when the 4800 beats the 955 which is not bandwith starved (although it does lack the L3 cache).
 

perplex

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Well from the reviews so far for Yonah it's quite impressive how it matches the AMD X2 clock for clock without an on-die memory controller and FSB architecture. This makes me think Intel won't be bringing out "CSI" (?) for a good few years yet?

Also, I thought Xeon was vastly inferior to Opteron in every aspect these days? :confused:
 

SLee

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perplex said:
Also, I thought Xeon was vastly inferior to Opteron in every aspect these days? :confused:
That's just the hype. The only real area that the Opteron is clearly superior in would be dualcore, 2 socket configurations which Intel will need Dempsy/Bensley to match. Otherwise, the Xeon is competitive. HT's current scalabilty is quite overrated, Opterons are known to scale poorly beyond 4 sockets for server type applications while IBM's X3 chipset for the Xeon MP scales well to 32 sockets.
 

Donnie27

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savantu said:
Tigerton will have 1 FSB/socket and I expect it to be 1333Mhz as Woodcrest hints...
4 sockets = 4 x1333 = 42 GBs to 8/16 cpus.That is truly a beast for a 4 socket machine.

As for the current Xeon MPs they are very competitive , in fact they beat any Opteron based server in most industry benchmarks.And they scale up to 32 sockets / 64 cores now.

IBM 366/460 are the most powerfull x86 based servers on the market.

But Opteron lives on thanks to the general hype...

http://www.theinquirer.net/?article=28533

Donnie27
 

perplex

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Then what the hell is all this "Opteron PIZOWNZ" horse sh*t(?) I keep reading Everywhere on the internet ? They make it sound like P4 vs Athlon 64 performance difference? So it's not true? :confused:
 

savantu

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perplex said:
Then what the hell is all this "Opteron PIZOWNZ" horse sh*t(?) I keep reading Everywhere on the internet ? They make it sound like P4 vs Athlon 64 performance difference? So it's not true? :confused:

That was true vs. the old Xeon MPs , aka Galatin core , 3Ghz/512kb L2/ 2-4MB L3 and 400Mhz FSB shared between 4 cores. :eek:

The new Xeon MP platform launched 1 year ago , has the Potomac core with 3.33Ghz/ 1MB L2 / 4-8MB L3 and a 667Mhz FSB shared between 2 cores.You can also use dual core CPUs like Paxville , 3Ghz 2x2MB L2 , 800Mhz FSB.
In Q4 this year we'll have Tulsa , 65nm , 800/1066FSB , 3.73Ghz+ , dual core , 2x2MB L2 , 16MB L3 shared.

Between the 2 platforms , FSB BW increased from 800MBs/core to 2.66GBs(3.2GBs with 800 FSB )/core and memory BW from 8.5GBs to 25.6GBs agregate.

It is easy to see why the new Xeon MP is able to compete with Opteron and outscore it in numerous benchmarks.

The new platform even surpassed Itanium 2 systems in 16 way benches like TPC-C...
 

perplex

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I see, thanks for clearing it up. I don't follow the server market as you could maybe guess.

I hope people know more than us about Intel's new FSB replacement, maybe that Intel employee? his/her name alias started with P.. :confused:
 

covertclocker

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:::AMD Troll::: ooooooooo boogey boogey boogey....

Now that I got that out of the way. OK, so Xeon beats Opteron in many benchies. Look at what it takes for Xeon to achieve this. Opteron isn't hype, it has delivered and more. Now, try to use an open mind if you can and figure how much more AMD would whomp on you guys if we did meet you on a clock for clock, spec for spec basis. I am talking cache, MHz, etc. We would be so far ahead Intel would just look silly. That and the immense power draws that you need to operate, and that is on the 65nm process. Sorry folks, you people are all crazy :confused:

:::runs back to AMD troll hole:::

EDIT - Few more things, whether or not you realize it, AMD has always been a few steps ahead of you guys for quite some time, 32/64bit on chips, intergrated mem controller, HyperTransport, busting of MHz myth, cooler, lower power consumption, etc. What has this left Intel to do, begrudgingly dragging their feet, they are slowly following in AMD's footsteps. While HyperThreading is a good idea, it has shown to hurt in some instances. I hope Intel can keep things interesting in the years to come, because it gets boring when you are always the winner. I am not saying that to flame bait. I am simply stating facts. When the benches came out for Dempsey, I knew AMD would still have a lead on it, and I didn't even have to know that it was on 65nm process to know that it would still be an energy hog. Intell needs to respond or AMD will be eating Intel's lunch and taking their lunch money along with it.
 

Dan_D

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Duke3d87 said:
I see your point. But, when you go to dual core, you still have a big problem; four cores (two dual core processors) sharing a 667 MHz FSB. And with the 21 GB/sec, that's only like 5 GB/sec/processor and the P4 lives off bandwith. I think it will get better, but I would have liked for Intel to release a 1 GHz+ FSB XeonMP to make them a bit more competitive

AMD still has a similar issue. Dual cores on 1 external HTT link still bottlenecks the CPU. Granted not by as much as the Xeon does now, or as it would with DIB and dual core Xeons. The Netburst architecture generally only bennefits from the largest of FSB increases though. Even with their castrated front side bus, they can still compete in some applications with the Opteron.

covertclocker said:
:::AMD Troll::: ooooooooo boogey boogey boogey....

Now that I got that out of the way. OK, so Xeon beats Opteron in many benchies. Look at what it takes for Xeon to achieve this. Opteron isn't hype, it has delivered and more. Now, try to use an open mind if you can and figure how much more AMD would whomp on you guys if we did meet you on a clock for clock, spec for spec basis. I am talking cache, MHz, etc. We would be so far ahead Intel would just look silly. That and the immense power draws that you need to operate, and that is on the 65nm process. Sorry folks, you people are all crazy :confused:

:::runs back to AMD troll hole:::

EDIT - Few more things, whether or not you realize it, AMD has always been a few steps ahead of you guys for quite some time, 32/64bit on chips, intergrated mem controller, HyperTransport, busting of MHz myth, cooler, lower power consumption, etc. What has this left Intel to do, begrudgingly dragging their feet, they are slowly following in AMD's footsteps. While HyperThreading is a good idea, it has shown to hurt in some instances. I hope Intel can keep things interesting in the years to come, because it gets boring when you are always the winner. I am not saying that to flame bait. I am simply stating facts. When the benches came out for Dempsey, I knew AMD would still have a lead on it, and I didn't even have to know that it was on 65nm process to know that it would still be an energy hog. Intell needs to respond or AMD will be eating Intel's lunch and taking their lunch money along with it.

True. The Xeon needs about 1GHz or more to be competetive with Opterons. Plus, the more CPU's there are in the box, the worse the Xeon's performance is. The Opteron clearly scales better with added CPU's.

savantu said:
Tigerton will have 1 FSB/socket and I expect it to be 1333Mhz as Woodcrest hints...
4 sockets = 4 x1333 = 42 GBs to 8/16 cpus.That is truly a beast for a 4 socket machine.

As for the current Xeon MPs they are very competitive , in fact they beat any Opteron based server in most industry benchmarks.And they scale up to 32 sockets / 64 cores now.

IBM 366/460 are the most powerfull x86 based servers on the market.

But Opteron lives on thanks to the general hype...

Not saying that the new Dual Independant Bus architecture won't help the Xeon. I am sure that it will. Still I have no idea to what benchmarks you are reffering to. I have read numerous benchmarks on Anandtech, the Techreport and other sites showing the Xeon only competing in two or three applications and getting it's ass handed to it the rest of the time. Paxville suffered a horrid defeat against the Opteron. Intel, and Xeon fans as well as many people in the IT profession are having a hard time coping with the Xeon's lack of performance compared to the Opteron. They rationalize to cope with the sadness. Sometimes even create elaborate delusions to show the Xeon in a better light.

Realizing you have a problem is the first step to recovery. :D
 

savantu

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Sir-Fragalot said:
...Still I have no idea to what benchmarks you are reffering to. I have read numerous benchmarks on Anandtech, the Techreport and other sites showing the Xeon only competing in two or three applications and getting it's ass handed to it the rest of the time. Paxville suffered a horrid defeat against the Opteron. Intel, and Xeon fans as well as many people in the IT profession are having a hard time coping with the Xeon's lack of performance compared to the Opteron. They rationalize to cope with the sadness. Sometimes even create elaborate delusions to show the Xeon in a better light.

Realizing you have a problem is the first step to recovery. :D

I'm talking medium business to enterprise , big boys stuff => 4 way and up servers which cost over 25k $

You're reffering OTOH to the Xeon DP which truely , has its ass delivered on a plate against the Opties...


Apples and oranges....
 

coldpower27

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covertclocker said:
:::AMD Troll::: ooooooooo boogey boogey boogey....

Now that I got that out of the way. OK, so Xeon beats Opteron in many benchies. Look at what it takes for Xeon to achieve this. Opteron isn't hype, it has delivered and more. Now, try to use an open mind if you can and figure how much more AMD would whomp on you guys if we did meet you on a clock for clock, spec for spec basis. I am talking cache, MHz, etc. We would be so far ahead Intel would just look silly. That and the immense power draws that you need to operate, and that is on the 65nm process. Sorry folks, you people are all crazy :confused:
What the point of saying if the AMD processors met the Pentium 4 Xeon on a clock for clock, cache for cache basis, the K8 architecture is simply not able to reach the clock frequnecies of the NetBurst architecture when both are on the same optical node such as 130nm or 90nm, also Intel has better cache technology then AMD, they can simply afford to throw larger amount of cache then AMD can given the same amount of die area and the same optical process hence why typically AMD has less cache then Intel on a process, they can't use as much because ti would cost them more.

To give you the same perspective, if the Pentium 4 Xeons had scaled to 10 GHZ as promised they would be blowing the Opterons out of the water :D.
 

StealthyFish

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lol, to address the guy on the top of this page... Intel had 64-bit before AMD... they were working on it like 20 years ago......... I haven't heard of any AMD chip that's going to be 65nm.... u guys even have a fab plant to make it?
 

empoy

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can we get rid of the fan boy infestation? hehehe just kidding.

ok so the current Xeon line sucks but we now have the Sossaman (Yonah for server) platform as Xeon LV.

as for Intel's answer to HyperTransport, I think we should see something by 2008. haven't seen any details yet.
 

Duke3d87

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empoy said:
can we get rid of the fan boy infestation? hehehe just kidding.

ok so the current Xeon line sucks but we now have the Sossaman (Yonah for server) platform as Xeon LV.

as for Intel's answer to HyperTransport, I think we should see something by 2008. haven't seen any details yet.
Why is it taking so long? Didn't the processor that got canceled right before the P4 using the integrated memory controller? You also forgot to mention Dempsey.
 

empoy

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dempsey is based from P4 architecture so let's forget about that.

there are a lot of tweaks in the microarchitecture that would negate the need for an integrated memory controller. it would also peg your architecture to a certain memory architecture. the previous project (Timna) had a rambus architecture. well we all know the story bet. Intel and Rambus.
 

Duke3d87

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empoy said:
dempsey is based from P4 architecture so let's forget about that.

there are a lot of tweaks in the microarchitecture that would negate the need for an integrated memory controller. it would also peg your architecture to a certain memory architecture. the previous project (Timna) had a rambus architecture. well we all know the story bet. Intel and Rambus.
so i'm going to assume that Intel is going to tweak the micro architecture so that it performs very well over the next year or two? And then when they unleash CSI, it will perform much better then AMD? I think RDRAM and Intel would have went on if it wasn't for Samsung and i think it was hynix's pricefixing
 

perplex

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I don't think Intel has officially mentioned CSI? I know it was scrapped with that Xeon but since then has it been mentioned? If not then I think it'll be a long time for a replacement to appear, seeing as how Intel next generation Merom will go into 2007 and beyond.
 

Duke3d87

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perplex said:
I don't think Intel has officially mentioned CSI? I know it was scrapped with that Xeon but since then has it been mentioned? If not then I think it'll be a long time for a replacement to appear, seeing as how Intel next generation Merom will go into 2007 and beyond.
They've talked about it for Itanium2 and Xeon class processors, but the trend tends to move so that what high end servers get, end users gets. Besides, they are all based on similiar cores to logically, they would be released around the same time. The team in India screwed up so they moved the project elserwhere.
 

pxc

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perplex said:
I don't think Intel has officially mentioned CSI? I know it was scrapped with that Xeon but since then has it been mentioned?
Where did you get your information? :p

Intel has officially mentioned CSI several times at IDF and even in their official magazine: http://www.intel.com/technology/magazine/computing/pawlowski-qa-1205.htm
Cache topography and interconnections are important portions of our architecture. Will you please discuss Intel's plan for improving these technologies?
...We're developing and researching different technologies, including CSI and optical—optical not only on the backplane, but eventually in the chip.

CSI for Xeon wasn't "scrapped", the rumor (if you believe theinq) is that Whitefield (or replacement) is delayed until 2008. Speculation before that was CSI would come to Xeons in 2007. http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=60404677
 

$BangforThe$

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Man AMD people are way more aggressive than Intel type's I had to check to see if I was in the intel forum. :) LOL
 

perplex

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*bump*

Anyone heard anymore? :confused: With Dell's decision about AMD it looks like Intel can't afford to delay or scrap their "CSI" and need to bring it out as soon as possible.

Will Nehalem have CSI ~2008, or? :confused:
 

savantu

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perplex said:
*bump*

Anyone heard anymore? :confused: With Dell's decision about AMD it looks like Intel can't afford to delay or scrap their "CSI" and need to bring it out as soon as possible.

Will Nehalem have CSI ~2008, or? :confused:


Uh no...

Intel asked wonders from the CSI group.They failed to reach any of those. :D
Whitefield got kicked you know where because Indians weren't able to integrate the core with CSI.. and on top of that Intel sacked 25% of its Indian designers for fraud. ;)

CSI is going to have less latency than HT , supposedly similar or more BW as Intel tells the OEMs.

Tukwilla will be the 1st product to use CSI , 4 full links and 2 half links for I/O.

As for Nehalem , all the odds are for it having CSI and IMC.
 

evilmedic

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savantu said:
http://www-03.ibm.com/servers/eserver/xseries/benchmarks/

Look there for IBM 366 and 460.
They have quitte a few records...

TPC-C , SpecJBB , TPC-H , SAP SD , etc...

Best TPC-C 8 way ( 4 way dual core ) is over 250k for Xeon and about 220k for Opteron.

Well, the the biggest problem with TPC-C is the its pretty much only used for "benchmarketing" Problems with TPC-C include
a. The transaction done in the benchmark trivial and do not reflect real world loads.
b. There is heavy emphesis on I/O system and more exactly. spreading many tiny I/O's over many many disks.

Lets take a look at the TPC benchmark for the x366 which got 221,017 TPC
http://www.tpc.org/results/individual_results/IBM/ibm.x366-DB2.c5.5.103105.es.pdf

Just look at that I/O subsystem... 784 x 36.6 15K RPM disks......28TB of disks....Look at that configuration,...... The ibm x366 only costed $156,000 the disksh costed 1.7 million...TPC-C benchmarks configurations that are just plain silly.
 

MrGuvernment

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I love people who when they talk about AMD (i guess some intel people do it too), they say
".....We would be so far ahead Intel would just look silly....."
As if they work for AMD or something :) "We" , So do you work for AMD ? or are you just that hardcore of a follower ?

and then refer to Intel people as "you" ........
"AMD has always been a few steps ahead of you guys for quite some time,... "
 
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