Intel to disable TSX in Haswell & Early Broadwell CPUs

CrimsonKnight13

Lord Stabington of [H]ard|Fortress
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The Tech Report said:
The TSX problem was apparently discovered by a software developer outside of Intel, and the company then confirmed the erratum through its own testing. Errata of this magnitude aren't often discovered this late in the life of a CPU core.

As is customary in such cases, Intel will disable the TSX instructions in current products using a CPU microcode update delivered via new revisions of motherboard firmware. Disabling TSX should ensure stable operation for Haswell CPUs, but those chips will no longer be capable of supporting TSX's features, including hardware lock elision and restricted transactional memory.
Source: http://techreport.com/news/26911/errata-prompts-intel-to-disable-tsx-in-haswell-early-broadwell-cpus

I'm definitely not a programmer or an engineer, but I do know that it sucks when you find errata in hardware that has to be disabled. It appears that TSX hasn't hit mainstream, so this may not affect most people anyways.
 
Intel says in the second update that TSX will be enabled in Haswell-EX, which isn't that far off. I wonder how long ago this bug was really detected.
 
It is my understanding that TSX is really for severely parallel data processes, so like massive databases so in reality you might not even see in in a consumer workload. I would like to see how to recreate the bug however.
 
It is my understanding that TSX is really for severely parallel data processes, so like massive databases so in reality you might not even see in in a consumer workload. I would like to see how to recreate the bug however.

I'm guessing it's so minor that it wasn't worth talking about till now!
 
That's 3 Intel generations in a row with defects.

Doesn't every single generation from AMD and Intel have defects? Although some defects are more meaningful than others and there is often a workaround for the errata. This one was a new feature that I suspect few use at this point.
 
Doesn't every single generation from AMD and Intel have defects? Although some defects are more meaningful than others and there is often a workaround for the errata. This one was a new feature that I suspect few use at this point.

Let's not bring up the defects from AMD, bulldozer was pretty much one big defect.
 
Didn't anyone else think that this was the coolest feature of Haswell? I mean, otherwise it's basically Sandy/Ivy in an incompatible socket... Maybe there aren't all that many active programmers here? I just got a Z87/G3258 combo with the thought of picking up a `real' Haswell later, kind-of blows if they're going to fix it in some later Broadwell stepping. =(

Granted, this stuff is pretty tricky, but to have an errata that the `workaround' is to entirely disable the feature sucks (I'm looking at you x58/5520 in regards to VT-d!).
 
4790K has TSX. Yes, it has better TIM as well, but I'm happy enough with my current OC + temps.
I feel bad for those who chose the 4770 over the 4770K specifically for TSX though.

TSX is being disabled because it fails under certain use cases.

Unpredictable microcode features are much worse than disabled microcode features.... which is why it has been disabled.

Any serious enterprise users who still have TSX enabled should update and disable it ASAP.
 
Any serious enterprise users who still have TSX enabled should update and disable it ASAP.
Other than proprietary applications and a couple of somewhat new libraries, virtually nothing uses TSX. I'd be very surprised if any significant numbers of enterprise users have any applications using it at all. It's not an automatic feature.

I'd bet there are more users who are actually using it and will avoid the microcode update disabling it than there are users actually using it and want to disable it. ;) In most cases, it's not being used and the microcode update disabling it won't be significant.
 
Other than proprietary applications and a couple of somewhat new libraries, virtually nothing uses TSX. I'd be very surprised if any significant numbers of enterprise users have any applications using it at all. It's not an automatic feature.

I'd bet there are more users who are actually using it and will avoid the microcode update disabling it than there are users actually using it and want to disable it. ;) In most cases, it's not being used and the microcode update disabling it won't be significant.

That was sort of my point. The post to which I replied was suggesting that it was good that he had a version where TSX was enabled....

My point was that is either doesn't matter at all or is actually harmful to keep it enabled.
If you have code which uses TSX it would be better for you not to use TSX until it's repaired.
 
Didn't anyone else think that this was the coolest feature of Haswell? I mean, otherwise it's basically Sandy/Ivy in an incompatible socket... Maybe there aren't all that many active programmers here?

There are tons here.
 
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That was sort of my point. The post to which I replied was suggesting that it was good that he had a version where TSX was enabled....

My point was that is either doesn't matter at all or is actually harmful to keep it enabled.
If you have code which uses TSX it would be better for you not to use TSX until it's repaired.
Rather the opposite. I was implying that one of the "good" points of the 4790K over the 4770K (in addition to improved TIM and higher baseclock) was TSX. That advantage has now been negated.
 
Haswell-EX models will have TSX enabled. I wouldn't hold my breath for it coming back to other models any time soon:

Update: An Intel spokesperson has provided TR with a brief statement on the TSX erratum, confirming that Intel has "addressed the issue" and "disabled the TSX feature on affected products." He further stated that Intel is "committed to the feature" over the long run and plans to "re-implement it in future processors." We have inquired about how the TSX erratum will affect upcoming Haswell-EP-series server CPUs and will post another update if we learn more.

http://techreport.com/news/26911/errata-prompts-intel-to-disable-tsx-in-haswell-early-broadwell-cpus

The 5960X is a Haswell-E(P), so TSX will be disabled in initial release microcode.
 
yikes, from wiki

According to benchmarks, TSX can provide around 40% faster applications execution in specific workloads, and 4–5 times more database transactions per second (TPS).[17][18][19][20]
 
I imagine Intel had to make a new stepping for Haswell-EX to fix the TSX errata, meaning that Haswell-EX production is probably temporarily suspended until the new stepping is ready (if it isn't already). That being said, I wonder what Intel's going to do with the large stockpile of Haswell-EX dies from the original stepping that they've accumulated so far that carry this flaw (that exceeds demand for 18, 16 and 14-core E5s). Let's just say I have a suggestion for the use of these dies...:D
 
More likely Haswell-EX had a "1.x" revision of the original TSX feature by design (given its later date), and was tested more thoroughly as a high end server chip. I really don't buy that Intel only discovered the problem a few months ago. The Haswell-EX design cycle shows the flaw was probably found over a year ago.

Intel's comments suggest the TSX feature is broken in regular Haswell and Broadwell models, and it's not going to take a revision to fix the problem. Specifically, Intel mentioned it will be reimplemented in future products.
 
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