Intel Says UCIe to Outpace PCIe in Speed Race

[kac77]

Intel Says UCIe to Outpace PCIe in Speed Race
-hpcwire.com

Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package.

 

[Zarathustra[H]]

Let me guess, it is going to be a proprietary Intel standard, completely fucking up the PC Norma of parts interchageability.

 

[LukeTbk]

Let me guess, it is going to be a proprietary Intel standard, completely fucking up the PC Norma of parts interchageability.

U if for universal apparently
Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC

With Arm and RISC it would have been surprising to be Intel proprietary, no ?

 

[Nobu]

U if for universal apparently
Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC

With Arm and RISC it would have been surprising to be Intel proprietary, no ?

So PCIe still exists, this is a separate technology for inter-die communication on a substrate/interposer?

Edit: Yep, from the article's gaping maw:

The comparisons were relative to distance. UCIe is designed for a very short distance on a substrate at the chip level, while PCI Express is implemented at the motherboard level, in which data is transferred over a longer distance and electrical requirements are different, Brennan said.

 

[Lakados]

Let me guess, it is going to be a proprietary Intel standard, completely fucking up the PC Norma of parts interchageability.

It’s an open standard that Intel heads up the board of.
https://www.uciexpress.org/specification
The members list is impressive to say the least.
https://www.uciexpress.org/membership

Here’s the thread on it from March when they announced it.
https://hardforum.com/threads/intel...l-interconnect-standard-for-chiplets.2018067/

This is the culmination of their 5 years of work into their Lego block chiplet construction.
The goal to standardize and bring down the packaging costs on chiplets for both designers and fabricators.