- Dec 19, 2005
"The "Grand Ridge" silicon is slated to be built on Intel's 7 nm HLL+ silicon fabrication node, and features 24 "Gracemont" cores across six clusters with four cores, each. Each cluster shares a 4 MB L2 cache among the four cores, while a shared L3 cache of unknown size cushions transfers between the six clusters. Intel is deploying its SCF (scalable coherent fabric) interconnect between the various components of the "Grand Ridge" SoC. Besides the six "Gracemont" clusters, the "Grand Ridge" silicon features a 2-channel DDR5 integrated memory controller, and a PCI-Express gen 4.0 root complex that puts out 16 lanes. It also features fixed function hardware that accelerates network stack processing. There are various USB and GPIO connectivity options relevant to 5G base-station setups. Given Intel's announcement of a delay in rolling out its 7 nm node, "Grand Ridge" can only be expected in 2022, if not later."