Intel 10nm/7nm CPU/GPU Rumor Thread : Cannonlake, Icelake, Tigerlake, Sapphire Rapids, etc.

Of course, it was originally planned for about 2015. The node transition was very aggresive and the plans failed miserably. We all know that. It is repeated in media and forums again and again.

What is not mentioned so often (in fact it is literally ignored) is that Glofo also planned 10nm for about 2015 and not only delayed it but canceled it twice (first canceled 10XM in 2016 then canceled 10LP about a year ago) and now goes for 7LP directly. And don't forget that what other foundries call 7nm is an inferior node to what Intel calls 10nm.

7nm is still a hell of a lot better than 14nm. Egg in the hand is worth two in the bush. Even 12/11nm could be argued to be better than 14nm in some aspects.
 
Bingo. And to top it all off their current 14nm process will still be better in a lot of aspects, compared the competition. Intel sucks, but their process nodes don't...

Not sure if serious?
 
Since Intel absolutely does not suck against the competition (considering performance), I had the same thought..

Those are clearly 2 different sentences, punctuation is hard I guess? Intel sucks as a whole, from consumer perspective.
 
punctuation is hard I guess?

At 46 I really don't care any more. I don't write papers for a living ( at least for the last decade ). I mostly write code for a living. With that said my name does appear in medical research journals and papers.
 
You need to clarify that very loose statement?
He's right. Intel's marketing department decides the consumer line up, and they ignore feedback from those consumers. They had a winner with Skylake-X processors, and then they shit all over the chipset features and did things that no consumer wanted. The decade of quad cores. Thick TIM layers. Broadwell pricing. The 14nm motherboard upgrade refresh cycle. You might think they are a company ran purely by profitability metrics from a piece of software.
 
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Those are clearly 2 different sentences, punctuation is hard I guess? Intel sucks as a whole, from consumer perspective.

The confusion was that "process node" was referring to a technical aspect. When you mentioned Intel, it was assumed you met the technical aspect of their architecture as well, not their buisness practices.

 
dont want 10nm unless it can clock well. we want 10nm++, let a 16 cores cpu run at 5ghz with standard 240mm water cooler.
 
10nm is a disaster for Intel, with now a almost end of 2019 launch they are in a serious bind. Intel has never fallen behind before and their reputation as a Industry leader will take a beating for it.
 
What makes matters even worse us that they are releasing Skylake v4.0 instead of a 14nm++ of Icelake which is a new architecture. As least release the new architecture so the bugs could be worked out by the time ICL releases.
 
10nm is a disaster for Intel, with now a almost end of 2019 launch they are in a serious bind. Intel has never fallen behind before and their reputation as a Industry leader will take a beating for it.

What makes matters even worse us that they are releasing Skylake v4.0 instead of a 14nm++ of Icelake which is a new architecture. As least release the new architecture so the bugs could be worked out by the time ICL releases.

not that i care, of course we want 10nm and we know its an issue. once its out, 10nm+ and 10nm++ will come out just like 14nm++ did. remember when 14nm came out broadwell couldnt clock well either and it had a lot of issue, 5775c was very limited, and can only clock to around 4.3ghz it was crappy. of course i dont think 14nm back then is as bad as 10nm now we just need to wait until it finally ship.

got a good feeling that this time around intel will give as much as optimization/ipc and power efficiency as well as binning as possible, because they know AMD is right up theirs.
 
All that I can say is that the holiday 2019 products better be Icelake as they did not say which 10nm product. It would be pretty pathetic if they launch desktop Cannondale aka Skylake v5.0
 
All that I can say is that the holiday 2019 products better be Icelake as they did not say which 10nm product. It would be pretty pathetic if they launch desktop Cannondale aka Skylake v5.0

10nm is a good bonus in terms of ipc optimization because smaller, also more power efficient, however i'd take 14nm+++ over it anyday just so i can clock it to 5.5ghz.

on another note. 8 cores!!!!!!
https://videocardz.com/76849/asrock-confirms-8-core-intel-cpu-support-for-h310-motherboard
 
Bingo. And to top it all off their current 14nm process will still be better in a lot of aspects, compared the competition. Intel sucks, but their process nodes don't...

Intel 14nm nodes have the performance lead, but they cannot compete with TSMC 10/7nm neither with Glofo 7nm in density. Intel needs to launch 10nm so soon as possible to compete with forthcoming 7nm TSMC/Glofo products.
 
10nm is a disaster for Intel, with now a almost end of 2019 launch they are in a serious bind. Intel has never fallen behind before and their reputation as a Industry leader will take a beating for it.

10nm is a disaster, but it is a well-managed disaster. Intel owns server, HPC, desktop, and mobile markets, despite all the hype around AMD's Zen.

It is funny to read people hyping Lisa Su for AMD comeback, when the 'comeback' is mostly a result of Intel 10nm delays.

Remember that 8-core Zen launched against 4-core Kabylake, 16-core Threadripper against 10-core Skylake-X and 32-core EPYC against 28-core Skylake-SP. Things had been very different for AMD if 8-core Zen had launched against 8-core Icelake.
 
Ipc is completely independent of node size. Clock speed is somewhat tied to node size.

sorry man i'd have to disagree there. more compact means closer together, higher density as well as lower latency. plus, i can only think of intel optimize it more, not less at this point in order to compete against AMD.
 
IPC is independent of node size.

thats what people say, but i believe otherwise. since decades, we have been moving stuff towards cpu. L1/L2 now L3 cache, long ago i believe some were even on motherboard and not on the chip, but slowly overtime all move towards it. shorter the distance, less resistance, lower the latency in general, just by logic.

a node shrink may not show enough benefit to count as measurable and be within margin of error. now unless of course if node shrink but doesn't actually reduce the size of die thats another matter.
 
thats what people say, but i believe otherwise. since decades, we have been moving stuff towards cpu. L1/L2 now L3 cache, long ago i believe some were even on motherboard and not on the chip, but slowly overtime all move towards it. shorter the distance, less resistance, lower the latency in general, just by logic.

a node shrink may not show enough benefit to count as measurable and be within margin of error. now unless of course if node shrink but doesn't actually reduce the size of die thats another matter.

IPC is independent of node size. You seem to confound latency in cycles with latency in nanosecond. Sorther the distance, shorter the latency in nanosecond, but the number of cycles is the same.

IPC is the inverse of CPI (Cycles Per Instruction): IPC = 1 / CPI.

If a division operation takes 30 cycles on a execution unit, when data is available to the unit. Then shrinking that unit on a new node will not change the cycles it needs to perform the division operation. It will continue being 30 cycles in 32nm and 30 cycles on 10nm.

If data needed to perform the division is not available on the register file, then the operation is delayed and a query to access the data is performed on the L1 cache. If the L1 cache takes 4 cycles to return the data. Then shrinking the cache on a new node will not change the cycles it needs to return the data. It will continue being 4 cycles in 32nm and 4 cycles on 10nm.

So the execution of the operation (including query to L1) will take 34 cycles in 32nm and 34 cycles on 10nm. CPI is the same, so IPC is the same.

Another thing is that node shrink gives the opportunity to introduce more stuff in the die. You can add more cache, larger table branch predictors, more execution units,... and that increases IPC. In this case you are using a node shrink to upgrade the microarchitecture and increase the IIPC, but the same microarchitecture on two different nodes has the same IPC.

Precisely Francois Piednoil suggested their bosses/peers that Icelake would be ported back to 14nm due to the delays on the 10nm node. If his suggestion was approved, we would now have a new microarchitecture in 14nm with IPC improvements over Skylake. It was rejected, and now we have to wait to 2019/2020 to see IPC changes.
 
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I didn't know that 14nm Icelake was suggested. Perhaps the spectre/meltdown fixes are taking as long as 10nm?

oleNBR - if die shrinks even had a few percent IPC improvements, we would simply be on Sandy Bridge v7.0 instead of Intel spending millions developing Haswell and Skylake.
 
10nm is a disaster, but it is a well-managed disaster. Intel owns server, HPC, desktop, and mobile markets, despite all the hype around AMD's Zen.

It is funny to read people hyping Lisa Su for AMD comeback, when the 'comeback' is mostly a result of Intel 10nm delays.

Remember that 8-core Zen launched against 4-core Kabylake, 16-core Threadripper against 10-core Skylake-X and 32-core EPYC against 28-core Skylake-SP. Things had been very different for AMD if 8-core Zen had launched against 8-core Icelake.

Well then it should be an interesting competition because intel will be going up against Zen 2 with a 15% IPC increase making it more than competitive.

And Lisa Su does deserve credit. She changed the direction of that company. It wasn't just because of Ryzen.

Bring on the competition. We all win.
 
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IPC is independent of node size.

It seems to me that many see 'IPC' and think 'Single-core performance', given that these are closely related and correlate well. Your explanation is pretty clear in deconstructing such confusion, but I wanted to point out where people may be coming from when they conflate the two.
 
IPC is independent of node size. You seem to confound latency in cycles with latency in nanosecond. Sorther the distance, shorter the latency in nanosecond, but the number of cycles is the same.

IPC is the inverse of CPI (Cycles Per Instruction): IPC = 1 / CPI.

If a division operation takes 30 cycles on a execution unit, when data is available to the unit. Then shrinking that unit on a new node will not change the cycles it needs to perform the division operation. It will continue being 30 cycles in 32nm and 30 cycles on 10nm.

If data needed to perform the division is not available on the register file, then the operation is delayed and a query to access the data is performed on the L1 cache. If the L1 cache takes 4 cycles to return the data. Then shrinking the cache on a new node will not change the cycles it needs to return the data. It will continue being 4 cycles in 32nm and 4 cycles on 10nm.

So the execution of the operation (including query to L1) will take 34 cycles in 32nm and 34 cycles on 10nm. CPI is the same, so IPC is the same.

Another thing is that node shrink gives the opportunity to introduce more stuff in the die. You can add more cache, larger table branch predictors, more execution units,... and that increases IPC. In this case you are using a node shrink to upgrade the microarchitecture and increase the IIPC, but the same microarchitecture on two different nodes has the same IPC.

Precisely Francois Piednoil suggested their bosses/peers that Icelake would be ported back to 14nm due to the delays on the 10nm node. If his suggestion was approved, we would now have a new microarchitecture in 14nm with IPC improvements over Skylake. It was rejected, and now we have to wait to 2019/2020 to see IPC changes.

I didn't know that 14nm Icelake was suggested. Perhaps the spectre/meltdown fixes are taking as long as 10nm?

oleNBR - if die shrinks even had a few percent IPC improvements, we would simply be on Sandy Bridge v7.0 instead of Intel spending millions developing Haswell and Skylake.

that makes more sense thx for explaining in details

also i still couldn't give up the distance thing, because say a 32nm node would be much bigger than a 14nm node gate/tri gate. i mean if you could fit say 4-5x more transistor in the same amount of space even if amount of cycle doesn't change, it should still be faster, its how i perceive it.

then that means theres something else done here from broadwell 5775c to skylake 6700k, because there is a gain of 2-3% IPC while both at 14nm. did they remove extra uneeded stuff to increase the IPC?
 
Lisu Su didn't single-handedly fix everything, but I do think her style and background is exactly what AMD needed. No flash, just calm competence. I find it refreshing in this era of CEOs wanting to be rock stars.
 
Intel can and will fix this. The problem with them is if they care enough to improve performance enough due to competition. We all see what happens when they stagnate due to lack there of. Ryzen 2 sounds like they will have a fire under them again. Like others have stated, we all win.
 
Well then it should be an interesting competition because intel will be going up against Zen 2 with a 15% IPC increase making it more than competitive.

And Lisa Su doesn't deserve credit. She changed the direction of that company. It wasn't just because of Ryzen.

Bring on the competition. We all win.

While the IPC gains are nice and welcome, if they can't increase the clockspeed of the CPU they will still be behind intel.
 
Intel can and will fix this. The problem with them is if they care enough to improve performance enough due to competition. We all see what happens when they stagnate due to lack there of. Ryzen 2 sounds like they will have a fire under them again. Like others have stated, we all win.

If all you need is beeing behind to make a better product, how come AMD is still behind intel on CPU and Nvidia in GPU?

A company will sell tons more if the gains are there for the customer, hence why there are people still holding on to sandy bridge era CPU's who would have upgraded years ago for something 50-75% more powerfull if it existed.
 
If all you need is beeing behind to make a better product, how come AMD is still behind intel on CPU and Nvidia in GPU?

A company will sell tons more if the gains are there for the customer, hence why there are people still holding on to sandy bridge era CPU's who would have upgraded years ago for something 50-75% more powerfull if it existed.

You'd be surprised how close competition can put a fire under you. I honestly have no idea wtf you are arguing about though?
 
I didn't know that 14nm Icelake was suggested. Perhaps the spectre/meltdown fixes are taking as long as 10nm?

https://www.fool.com/investing/2018/05/10/ex-intel-engineer-explains-the-companys-biggest-mi.aspx

oleNBR - if die shrinks even had a few percent IPC improvements, we would simply be on Sandy Bridge v7.0 instead of Intel spending millions developing Haswell and Skylake.

Correct, and Sandy Bridge would be simply a node shrink of the 45nm Nehalem, instead a "brand new microarchitecture" with radical changes compared to Nehalem.
 
Well then it should be an interesting competition because intel will be going up against Zen 2 with a 15% IPC increase making it more than competitive.

And Lisa Su does deserve credit. She changed the direction of that company. It wasn't just because of Ryzen.

Bring on the competition. We all win.

15% is a 'rumor' that is almost surely fake. Just because someone in a far away forum posts something anonymously, doesn't mean it is true. Recall all the fake leaks about Zen.

Lisa Su deserves credit, but she is being overhyped, just as Keller was before.

Competition is welcomed. I never said or insinuated the contrary.
 
that makes more sense thx for explaining in details

also i still couldn't give up the distance thing, because say a 32nm node would be much bigger than a 14nm node gate/tri gate. i mean if you could fit say 4-5x more transistor in the same amount of space even if amount of cycle doesn't change, it should still be faster, its how i perceive it.

If it takes one cycle for a signal to go from transistor A to transistor B, and you apply a node shrink, the signal cannot take 0.7 cycles to travel the reduced distance. It continues being 1 cycle. What has been reduced is the time t required to travel from A to B

t --> 0.7 t

That is, the frequency has increased. Indeed, whereas IPC doesn't depend on the node size, there is a direct relation between frequency F and node size

F = 1 / [ a + b S]

where "a" and "b" are parameters and "S" is a function of node size.

then that means theres something else done here from broadwell 5775c to skylake 6700k, because there is a gain of 2-3% IPC while both at 14nm. did they remove extra uneeded stuff to increase the IPC?

Skylake cores are new with improvements that increase IPC

Intel-Skylake-SP-Microarchitecture-Changes.jpg
 
Damn Francois advocated for 14nm ICL way back in April of 2016. Intel could have launched it today leaving ICL as a tock and finishing off DDR4 next year.

Now ICL will have to be DDR5 or else it will not share a platform with Tigerlake which will surely be DDR5.
That's what I've been worried about if icelake comes out in 2019. DDR5 and PCIe 4 are supposed to slowly ramp up for consumer products in 2020. 10nm might not be as fast as the current generation until 2020. Either icelake will only be compatible with a single motherboard platform at the end of 2019, or they will have to push back DDR5 and PCIe 4 for desktops to 2021. They may have to focus on Icelake-X bringing DDR5 and PCIe 4 support in 2020 to match the low volume of DDR5, along with minor 10nm improvements to get close to current generation speeds.
 
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Wasn't paper launch confirmed in some place?

im not sure, was just hoping that on august 1st, it'll be available to retailers guess thats obviously not the case otherwise preorders would have been available on many sites like a month ago.
 
im not sure, was just hoping that on august 1st, it'll be available to retailers guess thats obviously not the case otherwise preorders would have been available on many sites like a month ago.

Paper launch confirmed. 9th gen is 2019

Intel-Desktop-Roadmap_Mainstream-740x315.png
 
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