IBM Produces First Nanosheet Transistor for 5nm Silicon

[FrgMstr]

IBM and its Research Alliance partners GLOBALFOUNDRIES and Samsung have developed a first-of-a-kind process to build silicon nanosheet transistors that will enable 5 nanometer chips. The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT) and other data-intensive applications delivered in the cloud. The power savings could mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.

Check out the video.

The takeaway from this is that phones using this technology could go two or three days between charges and IBM suggest that we will see this technology in the next few years.

Pictured: a scan of IBM Research Alliance’s 5nm transistor, built using an industry-first process to stack silicon nanosheets as the device structure – achieving a scale of 30 billion switches on a fingernail-sized chip that will deliver significant power and performance enhancements over today’s state-of-the-art 10nm chips.

 

[Nukester]

This is just getting good. Star Trek here we come! Now if they can just figure out how to fold space, things could get interesting.

 

[grtitan]

I would love to see Ryzen on this process!!

 

[westrock2000]

Any words on transistor reliability? Will they last 10-20 years at this size?

 

[ianken]

"The resulting increase in performance will help accelerate #BUZZWORD, #BUZZWORD and other data-intensive applications delivered in the #BUZZWORD."

 

[TechLarry]

Looks like British dental x-rays.

Bwahahahaha.

Just kidding my English brothers

 

[Patton187]

Actually they now have better teeth.

 

[DejaWiz]

Holy shit... 5nm. My yearning for high performance power sipping CPUs and GPUs looms nearer.

 

[kandrey89]

The next advancement will come from lower power transistors that can be 3D layered on top of each other while using the silicon wafer as the primary support structure, that means each layer will increase the number of transistors one fold compared to the same die footprint. A sandwich of silicon transistor layers and heat laminate layers will prevent interlayer overheating by drawing heat from internal layers out to the side of the chip where they can be more efficiently coupled with the heatsink. Since the heat laminate will also be printed using the same process, layer interconnects will allow processor cores on different layers to interact thus enabling highly parallel 3D stacked processor units capable of up to ~12 fold increase in processing power. A stack greater than 12 layers will suffer degradation and failure due to heat stresses, different materials for transistors will need to be used to lower heat generation an order or two of magnitude, graphene transistors might be one solution.
To be clear, the 3D layers would not be built separately and then stacked like a TSV or other similar bonding schemes, each layer would be lithographically printed on the same wafer, utilizing the same technology in use today.

 

[Logan321]

Increases in power efficiency has never increased battery life, because manufacturers seem to have the "80% for a day of use" hardwired in their design process. If it uses 50% less power, they'll just put a 50% smaller battery in and make the phone another .25mm thinner.