Haswell TSX performance improvements

pxc

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This is pretty leading edge, but the results do point to some good things trickling down in the future to certain kinds of desktop loads:

http://sc13.supercomputing.org/schedule/event_detail.php?evid=pap260

Intel has recently introduced Intel Transactional Synchronization Extensions (Intel TSX) in the Intel 4th Generation Core Processors. With Intel TSX, a processor can determine dynamically whether threads need to serialize through lock-protected critical sections. In this paper, we evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads and demonstrate that applying Intel TSX to these workloads can provide significant performance improvements. On a set of real-world HPC workloads, applying Intel TSX provides an average speedup of 1.41x. When applied to a parallel user-level TCP/IP stack, Intel TSX provides 1.31x average bandwidth improvement on network intensive applications. We also demonstrate the ease with which we were able to apply Intel TSX to the various workloads.
 
Would Haswell with TSX possibly encroach on Ivy-E under certain workloads in the future?
 
Has anyone checked what the current status of TSX support is in glibc on Linux? AFAIK they had some issues with some of the more obscure requirements of the POSIX threads standard. This is something where Haswell might provide some immediate performance improvements on certain workloads under Linux.
 
https://github.com/andikleen/glibc

TSX lock elision for glibc v16

Proposed NEWS entry:

Added support for TSX lock elision for pthread mutexes and read/write locks on i386 and x86-64. This allows to improve lock scaling of existing programs. When the --enable-lock-elision=yes parameter is specified at configure time lock elision will be enabled by default for all PTHREAD_MUTEX_DEFAULT mutexes and rwlock.

...

Andi Kleen is on the job. ;)
 
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