GlobalFoundries unveils 12LP+ (real 12nm)

Nightfire

2[H]4U
Joined
Sep 7, 2017
Messages
2,158
This looks to be an overlooked tech story, but that is expected as it is not "cutting edge."
https://www.anandtech.com/show/1490...nology-massive-performance-power-improvements

Still, this new node looks promising and could alleviate some of the 7nm demand by shifting lower end products to use this new node.

This comes on the wake of even more supply issues of Intel's 14nm node.

Of course GF is not tied to either AMD or Intel. Wondering Intel finally outsource as this new node looks to be a perfect solution to Intel's problem...
 

Phelptwan

Supreme [H]ardness
Joined
Jul 20, 2002
Messages
6,522
Isn't this a big boon for things like Chipsets that are still predominantly in the 10+ world?
 
Joined
Apr 11, 2017
Messages
540
I wonder if GF is going to stay in the "2nd best" business and not go for cutting edge ever again...
 

Ready4Dis

Gawd
Joined
Nov 4, 2015
Messages
774
Plenty of work and chips could use 12nm... Not a bad position to be in. Lots of business, not as much risk, but not as much reward either. Should easily be able to make decent margins though.
 

ChadD

Supreme [H]ardness
Joined
Feb 8, 2016
Messages
4,562
Could be a nice node for AMDs Zen3 Controller chips. 12nm+ controller 7nm+ chiplets.
 

GoodBoy

[H]ard|Gawd
Joined
Nov 29, 2004
Messages
1,748
The 7nm/10nm/12nm++ etc is all a bit misleading. If you take the transistor count and divide it by the mm², you get transistors per square mm, or a standardized picture of the transistor density for each of the processes. Comparing those numbers across several of these 'processes' myself, I noticed the nvidia GPU's built on 16nm and 12nm were basically the same density.

And to top it all off, these numbers given as the "process size" are not at all in relation to "transistor size", which you would expect since transistor density is what the process size is purported to represent (maybe it isn't but that's what everyone has assumed). The ones I divided out it was a 14.5 to 15, to 1 ratio of process size to nm length on one edge of a transistor. (If my math was right).

One of the last densities I had calculated was 25.5 million transistors per mm², square root is 5050, so a square with:
5050 x 5050 transistors
1mm = 1,000,000 nm
so 1,000,000/5050 = 198nm

And this was one of the more recent, densest chips... either the 7nm AMD, maybe a 12nm GPU or CPU. The transistors are 198nm x 198nm... A rough generalization, maybe they are rectangles, but the point still stands. 198x198 = 39204 nm2 area for a single transistor. If they are rectangle its 100nm x 392nm.. so whatever the "process" is claimed to be, it's not at all the "transistor size".

I believe it is supposed to represent the smallest detail able to be created that make up the transistor as a whole.

Just pointing out that the 7nm vs 12nm isn't really telling us anything useful, in regards to density anyway.

The way the new chips are running (how hard navi is to oc, clocks speeds attained on Ryzen, both of which are 7nm parts) I am inclined to think the Intel process is the better process, as those chips reach higher speeds, even with it being 14nm+++ or whatever it is called.

(copy of my post in another thread, seems relevant here)
 

Ready4Dis

Gawd
Joined
Nov 4, 2015
Messages
774
The 7nm/10nm/12nm++ etc is all a bit misleading. If you take the transistor count and divide it by the mm², you get transistors per square mm, or a standardized picture of the transistor density for each of the processes. Comparing those numbers across several of these 'processes' myself, I noticed the nvidia GPU's built on 16nm and 12nm were basically the same density.

And to top it all off, these numbers given as the "process size" are not at all in relation to "transistor size", which you would expect since transistor density is what the process size is purported to represent (maybe it isn't but that's what everyone has assumed). The ones I divided out it was a 14.5 to 15, to 1 ratio of process size to nm length on one edge of a transistor. (If my math was right).

One of the last densities I had calculated was 25.5 million transistors per mm², square root is 5050, so a square with:
5050 x 5050 transistors
1mm = 1,000,000 nm
so 1,000,000/5050 = 198nm

And this was one of the more recent, densest chips... either the 7nm AMD, maybe a 12nm GPU or CPU. The transistors are 198nm x 198nm... A rough generalization, maybe they are rectangles, but the point still stands. 198x198 = 39204 nm2 area for a single transistor. If they are rectangle its 100nm x 392nm.. so whatever the "process" is claimed to be, it's not at all the "transistor size".

I believe it is supposed to represent the smallest detail able to be created that make up the transistor as a whole.

Just pointing out that the 7nm vs 12nm isn't really telling us anything useful, in regards to density anyway.

The way the new chips are running (how hard navi is to oc, clocks speeds attained on Ryzen, both of which are 7nm parts) I am inclined to think the Intel process is the better process, as those chips reach higher speeds, even with it being 14nm+++ or whatever it is called.

(copy of my post in another thread, seems relevant here)
This is why Intel isn't as far behind with 14nm vs tsmc 7nm... The # is only useful when you have more info to go along with it.
Just wanted to mention, Intel 14nm+++ has had a lot more refining, their first 14nm chip wasn't 5ghz all core :). 7nm will get better with 7nm+ or w/e they call it.
 

Armenius

Fully [H]
Joined
Jan 28, 2014
Messages
21,281
The 7nm/10nm/12nm++ etc is all a bit misleading. If you take the transistor count and divide it by the mm², you get transistors per square mm, or a standardized picture of the transistor density for each of the processes. Comparing those numbers across several of these 'processes' myself, I noticed the nvidia GPU's built on 16nm and 12nm were basically the same density.

And to top it all off, these numbers given as the "process size" are not at all in relation to "transistor size", which you would expect since transistor density is what the process size is purported to represent (maybe it isn't but that's what everyone has assumed). The ones I divided out it was a 14.5 to 15, to 1 ratio of process size to nm length on one edge of a transistor. (If my math was right).

One of the last densities I had calculated was 25.5 million transistors per mm², square root is 5050, so a square with:
5050 x 5050 transistors
1mm = 1,000,000 nm
so 1,000,000/5050 = 198nm

And this was one of the more recent, densest chips... either the 7nm AMD, maybe a 12nm GPU or CPU. The transistors are 198nm x 198nm... A rough generalization, maybe they are rectangles, but the point still stands. 198x198 = 39204 nm2 area for a single transistor. If they are rectangle its 100nm x 392nm.. so whatever the "process" is claimed to be, it's not at all the "transistor size".

I believe it is supposed to represent the smallest detail able to be created that make up the transistor as a whole.

Just pointing out that the 7nm vs 12nm isn't really telling us anything useful, in regards to density anyway.

The way the new chips are running (how hard navi is to oc, clocks speeds attained on Ryzen, both of which are 7nm parts) I am inclined to think the Intel process is the better process, as those chips reach higher speeds, even with it being 14nm+++ or whatever it is called.

(copy of my post in another thread, seems relevant here)
Two problems:
  1. You are assuming that all the transistors are tightly packed together.
  2. You are assuming that the size of the transistor defines the process node.
While it's true that transistor density is a function of transistor size, the size of the transistor itself is defined by the size and spacing of the gates. How gates are patterned in a transistor is the node process and is what (should) define the process node numbers we see. ITRS defines the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process, but as we know fabs fudge the numbers for marketing reason. It was made transparent by TSMC themselves that the 12nm process used in Turing was just a refinement of the 16nm process. Manufacturers used to use the gate length, but until recently gate length wasn't getting any smaller. I think with FinFET the fin pitch is more commonly used, but that information isn't readily available.

upload_2019-10-4_10-49-44.png
 

GoodBoy

[H]ard|Gawd
Joined
Nov 29, 2004
Messages
1,748
Two problems:
  1. You are assuming that all the transistors are tightly packed together.
  2. You are assuming that the size of the transistor defines the process node.

If you read my post I said "standardized picture of transistor density", and "rough generalization". There's probably space around the edge not used for transistors that used for connections, and there are likely other components that are not transistors at all. We still get a close estimate of the density, and from that the "rough" size... which was a square 198nm by 198 nm, nothing remotely close the to process size (12nm). That's the whole point I was making, which doesn't require explaining what measurement the "process size" actually indicates... a measurement that really doesn't matter, and has changed over time anyway.
 

Armenius

Fully [H]
Joined
Jan 28, 2014
Messages
21,281
If you read my post I said "standardized picture of transistor density", and "rough generalization". There's probably space around the edge not used for transistors that used for connections, and there are likely other components that are not transistors at all. We still get a close estimate of the density, and from that the "rough" size... which was a square 198nm by 198 nm, nothing remotely close the to process size (12nm). That's the whole point I was making, which doesn't require explaining what measurement the "process size" actually indicates... a measurement that really doesn't matter, and has changed over time anyway.
The point I was making was that process node never was a measurement of the size of the entire transistor. As I said, it was originally defined by the gate length. Ultimately, to your point, transistor density is more meaningful.
 

defaultluser

[H]F Junkie
Joined
Jan 14, 2006
Messages
13,131
Plenty of work and chips could use 12nm... Not a bad position to be in. Lots of business, not as much risk, but not as much reward either. Should easily be able to make decent margins though.

Assuming they can find customers. TSMC has been shipping products on their 12nm process for 18 months now. Used by Nvidia's Turing, and AMD's RX 590, so it must already be affordable AND plentiful!

You can assume that any demand for first-mover 12nm has already been met, and they will be left with the cruft. Such is the breaks, when you stop competing.

They may be able to negotiate the next revision of the AMD's memory controller, but they won't win any new business with that late arrival.
 
Last edited:

Nightfire

2[H]4U
Joined
Sep 7, 2017
Messages
2,158
Assuming they can find customers. TSMC has been shipping products a 12nm process for 18 months now. Used by Nvidia's Turing, and AMD's RX 590, so it must already be affordable AND plentiful!

You can assume that any demand for first-mover 12nm has already been met, and they will be left with the cruft. Such is the breaks, when you stop competing.
Are you serious? This 12nm node seems to be much more advanced than the current one. (marketing slide perhaps, but which ones are not) This could be great for lower end hardware for AMD. It would be a strange world if something like the next gen 4600x/4800x (edit) used a larger node than the current gen, but if it can clock higher, there would definitely be a market for it. Then they could save the overstressed 7nm line to cpus like the 4600/4700 non-x as well as higher core count cpus that are need to limit power draw on the platform.
 
Last edited:

Snowdog

[H]F Junkie
Joined
Apr 22, 2006
Messages
10,211
Assuming they can find customers. TSMC has been shipping products on their 12nm process for 18 months now. Used by Nvidia's Turing, and AMD's RX 590, so it must already be affordable AND plentiful!

You can assume that any demand for first-mover 12nm has already been met, and they will be left with the cruft. Such is the breaks, when you stop competing.

They may be able to negotiate the next revision of the AMD's memory controller, but they won't win any new business with that late arrival.

The TSMC 12nm that NVidia uses for 2000 series is has exactly the same transistor density as the TSMC 16nm process they used for 1000 series.
 

Sycraft

Supreme [H]ardness
Joined
Nov 9, 2006
Messages
4,592
This is why Intel isn't as far behind with 14nm vs tsmc 7nm... The # is only useful when you have more info to go along with it.
Just wanted to mention, Intel 14nm+++ has had a lot more refining, their first 14nm chip wasn't 5ghz all core :). 7nm will get better with 7nm+ or w/e they call it.
Not to say Intel has legitimately slipped with their process nodes, but also they have been a lot more honest with naming. Realistically TSMC should be calling 12nm "16nm+" or maybe "20nm++". They've been just jumping to the next half node number every time they refine their process, regardless of how much, if any, shrink there is in the features. Intel has been more honest in nothing that ya, it is a refined process with changes, but it is still the same feature size.
 

defaultluser

[H]F Junkie
Joined
Jan 14, 2006
Messages
13,131
The TSMC 12nm that NVidia uses for 2000 series is has exactly the same transistor density as the TSMC 16nm process they used for 1000 series.
And where did you get that stat? Pulled completely out of your ass!


Here they advertise a 20% area savings going TSMC 12nm vs 16nm, and 25% power:

https://www.anandtech.com/show/11337/samsung-and-tsmc-roadmaps-12-nm-8-nm-and-6-nm-added/4


The Global Foundries original 12lp was worse than TSMC 12nm (and 10 months behind it), and thus didn't get many customers:

http://www.globalfoundries.com/news...-technology-for-high-performance-applications

TSMC will have more than enough process capacity to meet 7nm demand within 3 months, so the window for this process node is rapidly closing. REMEMBER, Nvidia is ditching TSMC for Samsung for Ampere, so AMD and Apple will be their largest customers. THERE WILL BE A PRICE WAR ONCE THESE TWO FOUNDRIES ARE SPINNING, and that means lower prices for 7nm.

Once again, Global Foundries is desperately trying to remain relevant, while being two steps behind TSMC and Samsung!
 
Last edited:

Nightfire

2[H]4U
Joined
Sep 7, 2017
Messages
2,158
And where did you get that stat? Pulled completely out of your ass!


Here they advertise a 20% area savings going TSMC 12nm vs 16nm, and 25% power:

https://www.anandtech.com/show/11337/samsung-and-tsmc-roadmaps-12-nm-8-nm-and-6-nm-added/4


The Global Foundries original 12lp was worse than TSMC 12nm (and 10 months behind it), and thus didn't get many customers:

http://www.globalfoundries.com/news...-technology-for-high-performance-applications

TSMC will have more than enough process capacity to meet 7nm demand within 3 months, so the window for this process node is rapidly closing. REMEMBER, Nvidia is ditching TSMC for Samsung for Ampere, so AMD and Apple will be their largest customers. THERE WILL BE A PRICE WAR ONCE THESE TWO FOUNDRIES ARE SPINNING, and that means lower prices for 7nm.

Once again, Global Foundries is desperately trying to remain relevant, while being two steps behind TSMC and Samsung!
Dang, did GF piss in your Wheaties or something?

TSMC will have enough capacity in 3 months? That seems like a stat pulled from the rear.

With a 40% power reduction to an already popular node, it seems like a great refresh upgrade to legacy mainstream products. It also seems like consoles would make great use of it
 

Snowdog

[H]F Junkie
Joined
Apr 22, 2006
Messages
10,211
And where did you get that stat? Pulled completely out of your ass!
No I used this apparently largely unknown (around here) power I have, called: "Math", to calculate the transistor density of a 2080 Ti and 1080 Ti, and discovered they were essentially identical (~ 25 million transistors/mm^2).

Also the 12nm process you linked for TSMC is NOT the one NVidia uses for it's GPUs.
 

KATEKATEKATE

Limp Gawd
Joined
Jan 20, 2019
Messages
312
I wonder if GF is going to stay in the "2nd best" business and not go for cutting edge ever again...
GloFo pretty much confirmed a shift to "2nd-best" when they announced the cancelation of their 7nm process. They didn't explicitly rule out doing a 7nm process later when equipment & R&D costs are down but It sounds like GloFo's leadership is content to go for the volume on "good enough" 14/12nm class processes and let Samsung and TSMC be the ones to pour billions and billions and billions into new sub-10nm class nodes. 5nm is going to be super expensive and difficult to implement. 3nm or whatever comes after even more so.

https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development

I doubt this new 12nm process will see any high-performance use, more like I/O chips like folks have said, plus I forsee a lot of low/midrange smartphone SOCs using this process.
 
Top