Gateless Majority Logic

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
Photo shows a mix of SSOP and TSOP parts on the front.
For the moment, nothing but empty SOIC pads exist on back.
Individual slices need some wires between those SOIC pads.

Complete assembly might look like eight books on a DIP40 shelf.
A floppy pigtail might bring in power better than rely on DIP pins.

74LVC2G86 XOR gates load the chain about 5pF per slice.
74AUC2G86 XOR could reduce that to about 2.5pF per.
AUC would need a separate 2.7V rail or downregulator, can't
operate at same 5.5V as fastest voltage for CBT multiplexers.

I wonder if emitter followers could help buffer XOR inputs?
KSP10 claims less than 1pF. One base-emitter voltage drop
should be no problem for driving AUC logic's 0.8V threshold.
Even if it slows those final XORs, it might speed up the chain.

I say KSP10 cause I own a bag of 1000 or maybe it was 5000.
Maybe Schottky diodes were the 5000, something was 5000.
Arrow was closing out for under a penny, so why the hell not?
Some kinda gold doped RF transistor that refuses to saturate.
https://www.mouser.com/datasheet/2/149/KSP10-889509.pdf

Left myself no room on these slices to be thinking of buffers.
Where am I supposed to put those? Build as-is and measure.
Maybe there is no problem except I keep changing the plan.

EightSlices.jpg

XOR_MUX_XOR.png
 
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KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
ManchesterAssymetry.png


An issue of all my prior drawings was the very thin chain of single pass
gates driving cumulative fanout of inactive passages and XOR inputs.
Capacitance multiplied by 16bit length could become a real problem.

Main features of this drawing are parallel passages for the critical path.
That won't make the critical path any faster by itself, only more tolerant
of loads not slowing it down.

Generate and Annihilate logic are now screened off when not in play.
Don't require same ultra-low resistance as main path of Propagation.
Non-paralleled pass gates are preferred here for lower capacitance.
Can't make gates any lower capacitance than they are, but perhaps
make these appear small by comparison.

Was some guy building a 100MHz 6502, though so far only 25MHz.
Had similar chains of CBT3253. Reported measurement of that very
problem, but come to slightly diffferent conclusion how best to solve.

My attempts to contact Drass have not yet worked. Or maybe he has
correctly assessed that all my ideas are nuts and unworthy of reply?
https://c74project.com/
https://hackaday.io/project/174769-100mhz-ttl-6502

Drawing needs fixed again. Borrow backwards should be "Worrob".
Why did I reverse misspell? Nevermind, drawing fixed now...
 
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KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
And I just had another useless revelation
while staring too long at this damn borrow
and magnitude chain.

Invert: borrow in, borrow out, result out.
Another way to mutate A-B to B-A when
subtracting. Should work for other ALUs.

As relates to my ALU: I've got two new
subtraction functions to add to the menu.
Can now work with either inverted or non
inverted borrows simply by inverting the
direction at LT GT.

Setup with inverted truth inputs might be
a way to invert the result out, but I kinda
made that difficult by wiring S0 to GND.

Not updating the drawing right now, got
other fires to deal with. Just posting so
I won't forget...
 
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KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
Back to Majority logic for a moment...
No clue if this would actually work, only got 4 of these ICs in my junk drawer.
Coincidentally, Digikey is running some sort of a most useless 555 challenge.
I've got till Jan 10th to embarass myself, maybe not impossible.
555SerialMajorityALU.png

One very slow bit at a time here, but Carry feeds back for an unlimited width ALU.
Thinking Pi Pico to bit bang some numbers at it and record whatever comes out.
Not going to bother with ALU controls, just proving it can add should be enough.

Details to remember about 555s: /Reset overrides /Trigger overrides Threshold.
For bipolar 555, output high was VCC-1.7V. CMOS 555 now outputs VDD high.

For bipolar, Trigger level balances vs the average output mix at 1/3 of VCC5V.
Because VCC-1.7V, bipolar isn't going to mix right at any other supply voltage.
Maybe if you pull DIS up to VCC and abuse that terminal as-if a CMOS output.

For full CMOS output, the average vote would be too high. But we can fix that
by raising trigger level to 1/2 supply. Do that by wiring VDD and CV together.
Votes should now balance well vs trigger at any reasonable supply voltage.

Either way, Pi Pico can't output or accept input higher than its own VDD3.3V.
Which might work with Bipolar at VCC5V, or for sure with CMOS at VDD3.3V.
Intend to measure the actual Bipolar output before connecting my Pi to it.

VCC (Voltage of the Collector) implies Bipolar Junction Transistors.
VDD (Voltage of the Drain) implies Field Effect Transistors.
Otherwise describing equivalents.
 
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KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
The above plan was doomed. Because it allowed signal to propagate any time after reset, it doesn't hold back to one predictable forward step.
Like syncronus if logic happens to tip one way, asynchronus the other. Yeah, completely broken.

So what might fix this? Vote time (blue) should be restricted to a narrow upward pulse, separate from a downward pulse (yellow) which clears the previous vote.
Sync_Maj3.png

Output of real NE555 measures more like 0.2V to 4.5V, as forwarded by the Hi Lo input models. Not quite 0 to 5V output as simulated (red).

I have a slightly more complex version for compatability with Pi Pico's 3V IO, but the above should work for 5V NE555s talking to NE555's.
The 555 contest is long over by now, but I still find the unsolved challenge to be of interest.
 
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KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
698
Another useless development, the "impossible" asynchronus XOR gate in 555...
One input mixer simultaneously compares against different references with opposing results.
References differ by about 1 vote. XOR ( A , B ) = AND ( MAJ3 ( A , B , 0 ) , MIN3 ( A , B , 1 ) )
555XOR_AdNauseum.png

THRS has been set just above CV to output high by default. Only if both A and B vote high would this remain the result.
TRIG has priority over THRS. An A or B low vote vs CV/3 may attempt to pull the output low. Loser loses. Majority wins.
RST has ultimate priority. Unanimously low votes vs 0.7V may then push output back up. Loser takes all. Minority wins.
Almost rock scissors paper, except priorities don't quite make a complete loop. Paper won't attempt to cover rock.
Somehow or other, all this conspires to make XOR exactly as our founding fathers intended? Yeah verily...

I have actually built and proven this gate works, not just my usual hypertheatrical noodlings in LTSpice.
 
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