Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020

erek

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5nm!

"Thankfully in TSMC’s 5nm paper at IEDM, the topic of DTCO is directly addressed. The 5nm test chip has an element of DTCO applied, rather than brute-forcing the design rules, which has enabled scaling of the design rules for an overall 40% chip size reduction. So that overall test chip, at 17.92 mm2, would have been more like 25.1 mm2, with a yield of 73%, rather than 80%. It doesn’t sound like much, but in this case every little helps: with this element of DTCO, it enables TSMC to quote the 1.84x increase in density for 15+% speed increase/30% power reduction.

Unfortunately, we don't have the re-publishing rights for the full paper. For those that have access to IEDM papers, search for

36.7 5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with Densest 0.021 µm2 SRAM Cells for Mobile SoC and High Performance Computing Applications, IEEE IEDM 2019

One obvious data point that TSMC hasn't disclosed is the exact details on its fin pitch sizes, or contacted poly pitch (cpp), which are often quoted when disclosing risk production of new process nodes. We're hoping TSMC publishes this data in due course."


https://www.anandtech.com/show/1521...-h1-2020?utm_source=twitter&utm_medium=social
 
Impressed Thor 11122019233629.jpg
 
Holy carp 80% yield at this early point!!


On small chips. A full-sized mobile processor would be closer to 30%. But that's still impressive for a first go!

I do give them credit for building something more complex than just SRAM for the first process tests.
 
I was just tryin to figure how many silicon atoms wide 5nM might be?

But a scrape for answers loots different size depending where I read.
Yeah verily, various sources I read from two to five silicons per nM.
Or 0.5nM to 0.2nM. Density be that uncertain, can it? What gives?

If I slice a cubic crystal on the worst slant, I might find twice distance.
Distance x1.4 across hypootenanny of 2D square, x1.4 again 3D cube.
But I don't suspect funny cuts is how its done. Doesn't change density.
Dope and Oxide added to make transistors might, but do those count?

https://www.princeton.edu/~maelabs/mae324/glos324/silicon.htm
"The electronic configuration of the silicon atom is: (Ne)(3s)2(3p)2, and
the atomic radius is 0.132 nm.

Silicon has the diamond cubic crystal structure with a lattice parameter
of 0.543 nm. The nearest neighbor distance is 0.235 nm. The diamond
cubic crystal structure has an fcc lattice with a basis of two silicon atoms."


Possibly thee right nM answers? Still don't get which one applies here.
If I divide lattice parameter 0.543nM by the lattice basis of two atoms:
I get 0.2715. Which doesn't agree with nearest neighbor 0.235 at all.

Wait. Princeton don't capitalize the M in Meter. Small m for meter now?
Is that cause meter wasn't a personal name like Ampere, Volta or Watt?
Or was something else more important already camping on capital M?
 
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I was just tryin to figure how many silicon atoms wide 5nM might be?

But a scrape for answers loots different size depending where I read.
Yeah verily, various sources I read from two to five silicons per nM.
Or 0.5nM to 0.2nM. Density be that uncertain, can it? What gives?

If I slice a cubic crystal on the worst slant, I might find twice distance.
Distance x1.4 across hypootenanny of 2D square, x1.4 again 3D cube.
But I don't suspect funny cuts is how its done. Doesn't change density.
Dope and Oxide added to make transistors might, but do those count?

https://www.princeton.edu/~maelabs/mae324/glos324/silicon.htm
"The electronic configuration of the silicon atom is: (Ne)(3s)2(3p)2, and
the atomic radius is 0.132 nm.

Silicon has the diamond cubic crystal structure with a lattice parameter
of 0.543 nm. The nearest neighbor distance is 0.235 nm. The diamond
cubic crystal structure has an fcc lattice with a basis of two silicon atoms."


Possibly thee right nM answers? Still don't get which one applies here.
If I divide lattice parameter 0.543nM by the lattice basis of two atoms:
I get 0.2715. Which doesn't agree with nearest neighbor 0.235 at all.

Wait. Princeton don't capitalize the M in Meter. Small m for meter now?
Is that cause meter wasn't a personal name like Ampere, Volta or Watt?
Or was something else more important already camping on capital M?
Metric units are just all lowercase (well, with a few exceptions I'm sure). The prefixes for 10x 100x and 1000x (Deca, Mega, and Kilo, respectively) are capitalized, while the prefixes for .1x .01x and .001x (deci, centi, and milli) are not.
 
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I was just tryin to figure how many silicon atoms wide 5nM might be?

But a scrape for answers loots different size depending where I read.
Yeah verily, various sources I read from two to five silicons per nM.
Or 0.5nM to 0.2nM. Density be that uncertain, can it? What gives?

If I slice a cubic crystal on the worst slant, I might find twice distance.
Distance x1.4 across hypootenanny of 2D square, x1.4 again 3D cube.
But I don't suspect funny cuts is how its done. Doesn't change density.
Dope and Oxide added to make transistors might, but do those count?

https://www.princeton.edu/~maelabs/mae324/glos324/silicon.htm
"The electronic configuration of the silicon atom is: (Ne)(3s)2(3p)2, and
the atomic radius is 0.132 nm.

Silicon has the diamond cubic crystal structure with a lattice parameter
of 0.543 nm. The nearest neighbor distance is 0.235 nm. The diamond
cubic crystal structure has an fcc lattice with a basis of two silicon atoms."


Possibly thee right nM answers? Still don't get which one applies here.
If I divide lattice parameter 0.543nM by the lattice basis of two atoms:
I get 0.2715. Which doesn't agree with nearest neighbor 0.235 at all.

Wait. Princeton don't capitalize the M in Meter. Small m for meter now?
Is that cause meter wasn't a personal name like Ampere, Volta or Watt?
Or was something else more important already camping on capital M?


For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

1.4nm = 12 si atoms
(1.4nm / 1.4) = (12 / 1.4) si atoms
1nm = (12 / 1.4) si atoms
1nm = 8.57 si atoms

5nm = (8.57 x 5) si atoms

5nm = 42.86 si atoms
 
For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

1.4nm = 12 si atoms
(1.4nm / 1.4) = (12 / 1.4) si atoms
1nm = (12 / 1.4) si atoms
1nm = 8.57 si atoms

5nm = (8.57 x 5) si atoms

5nm = 42.86 si atoms

For 5nm=42.86si, each Si would be packed 0.117nm from its neighbor.
Which seems impossible, because that is less than Si's atomic radius.
At least, the atomic radius according to Princeton.

Of course, I get different numbers everywhere. Very different numbers.
A great many reliable sources do not seem to agree. Enough so, that
I cannot easily choose one to trust and dismiss all conflict.

On the another hand, Si does seem to have three layers of electrons.
Which one defines the radius? Which bonds Si with Si neighbors?

http://inst.eecs.berkeley.edu/~ee130/fa07/lectures/Semiconductor_fundamentals_lec1.pdf
Check out slide #6. Diagram makes a simple question not so simple.
Lets say we cut on the 100, as Berkley suggests is the typical way.
And the question then, is distance from corner Si to face center Si.

Which is very peculiar, because they seem closest, yet not bonded.
Given this latest link reports corner to corner dstance as 5.43A.
Now to cipher how do A (Angstroms?) convert to nm...

-edit- Crap, that was easy. 10 Angstroms to each nm. Go figure...
 
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So Princeton sais 0.543nm corner to corner. Berkley sais 5.43A.
We have an agreement of measure that I now feel OK to trust.
Now to make like Pythagoras for a few and get back to you.

-edit- Math suggests 0.384nm between closest Si on plane of
the cut, where some process is likely going to make transistors.
Thats what for 5nm? Like only 13 atoms., seems a low number.
Damn, and I would have believed 42 if hadn't just ciphered 13.

Yet no SI on said cut is bonded directly to its neighbor. Rather
each bonds to two Si below. Leaving two bonds unaccounted.
I dunno exactly what happens with those.

Something doesn't smell right bout 13 atoms. Just too few...
I gotta figure where this math has gone off the rails. I took
half the corner to corner and figured the hypotenuse to get
what I thought might be the distance corner to face center.
 
Last edited:
So Princeton sais 0.543nm corner to corner. Berkley sais 5.43A.
We have an agreement of measure that I now feel OK to trust.
Now to make like Pythagoras for a few and get back to you.

-edit- Math suggests 0.384nm between closest Si on plane of
the cut, where some process is likely going to make transistors.
Thats what for 5nm? Like only 13 atoms., seems a low number.
Damn, and I would have believed 42 if hadn't just ciphered 13.

Yet no SI on said cut is bonded directly to its neighbor. Rather
each bonds to two Si below. Leaving two bonds unaccounted.
I dunno exactly what happens with those.

Something doesn't smell right bout 13 atoms. Just too few...
I gotta figure where this math has gone off the rails.


some reference for you:

https://www1.columbia.edu/sec/itc/ee/test2/pdf files/silicon basics.pdf
 
Technically, atoms don't have a set diameter – it varies with energy level, other nearby atoms, what atoms they're bonded to, the kind of bond, the number of neutrons in the atom (if it's an ion/anion), etc..
 
Page 5 of that link confirms corner to corner distance as 5.431 unspecified units.
Sais Angstroms on next page. Columbia agrees with both Princeton and Berkley.

Distance between closest bonded Si (not same as closest neighbor on cut face)
was also given as 2.3517. Not an immediately useful figure as those bonds are
not at convenient 90 degree angles, but the cube corners certainly are.

Page17: Surface can lower energy by forming Si-Si bonds, creating rows of “dimers”.
Assuming the 100 cut only cornrows itself like that when you don't build anything on
top of it, or until. Don't know if that changes nature of the question, probably not...
 
Last edited:
Devices are 15 percent faster and 30 percent more energy efficient


https://spectrum.ieee.org/nanoclast/semiconductors/devices/tsmc-5-nanometer-process

Hmmm.. I think anandtech says its 15 percent faster OR 30 percent more efficient.
https://www.anandtech.com/show/1521...-h1-2020?utm_source=twitter&utm_medium=social
The Headline Numbers
If you’re only here to read the key numbers, then here they are. In the disclosure, TSMC is stating that their 5nm EUV process affords an overall with a ~1.84x logic density increase, a 15% power gain, or a 30% power reduction.
 
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I was just tryin to figure how many silicon atoms wide 5nM might be?

But a scrape for answers loots different size depending where I read.
Yeah verily, various sources I read from two to five silicons per nM.
Or 0.5nM to 0.2nM. Density be that uncertain, can it? What gives?

If I slice a cubic crystal on the worst slant, I might find twice distance.
Distance x1.4 across hypootenanny of 2D square, x1.4 again 3D cube.
But I don't suspect funny cuts is how its done. Doesn't change density.
Dope and Oxide added to make transistors might, but do those count?

https://www.princeton.edu/~maelabs/mae324/glos324/silicon.htm
"The electronic configuration of the silicon atom is: (Ne)(3s)2(3p)2, and
the atomic radius is 0.132 nm.

Silicon has the diamond cubic crystal structure with a lattice parameter
of 0.543 nm. The nearest neighbor distance is 0.235 nm. The diamond
cubic crystal structure has an fcc lattice with a basis of two silicon atoms."


Possibly thee right nM answers? Still don't get which one applies here.
If I divide lattice parameter 0.543nM by the lattice basis of two atoms:
I get 0.2715. Which doesn't agree with nearest neighbor 0.235 at all.

Wait. Princeton don't capitalize the M in Meter. Small m for meter now?
Is that cause meter wasn't a personal name like Ampere, Volta or Watt?
Or was something else more important already camping on capital M?
5nm is just a marketing term (I think at 28 nm they stopped bothering with nm relating to pitch sizes?).

Ah, here: https://en.wikichip.org/wiki/technology_node
Historically, the process node name referred to a number of different features of a transistor including the gate length as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held.
 
I read in the link from post#8: 20nm smallest thing they attempt to make with 5nm process.

Guess that makes sense. Since I am sometimes asked to test power transistors for basic
function before they go to characterization. Those cut from the edge are not in ideal focus.
Its important I keep track of which widget came from where. Though all look same to me.

20nm / 0.384nm = 52 Silicon atoms on the cut face. Not accounting for dimer cornrows...
 
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