Dual-CCD Ryzen 5 5600X and Ryzen 7 5800X In the Wild

erek

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"There are, apparently, some 5600X and 5800X built from dual-CCD MCMs, in which an entire CCD, although physically present on the package, is disabled. A 5600X based on a dual-CCD design is essentially a 5900X from which one of the CCDs didn't fully qualify; while the 5800X dual-CCD is a 5950X in which one such die didn't quite make the cut. There's no telling which CCD is disabled, it could be CCD 0 or CCD 1, those with CCD 0 disabled could trigger minor (benign) UI bugs with certain tuning utilities, which is how Wallossek and Bubliy discovered these chips. In any case, you're getting a 5600X or 5800X that works as advertised, and is fully covered by AMD's product warranties. Igor's Lab is investigating further into these dual-CCD 5600X and 5800X chips, and is probing the possibility of unlocking them to Ryzen 9."

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https://www.techpowerup.com/277053/dual-ccd-ryzen-5-5600x-and-ryzen-7-5800x-in-the-wild
 

mnewxcv

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No surprise. My question is are there cpus that aren't like this and really just have a "spacer" rather than a disabled ccd?
 

KATEKATEKATE

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No surprise. My question is are there cpus that aren't like this and really just have a "spacer" rather than a disabled ccd?
probably not on AM4... I think the spacers were necessary on TR4 to keep the massive IHS stable under hsf mounting pressure, no need for it on the smaller chips.
 

mnewxcv

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RanceJustice

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Neat to see. I don't know if it was possible, but I'd consider it possibly a benefit for AMD to disable those CCDs in a possibly "unlockable" way like they did in the old Athlon/Phenom days, vs more recent situations (for Intel and I think AMD) where they essentially burn out the traces or something, rendering it inoperable. AMD can remember that it thrived back in those days and mobos with attempting to "unlock" features were a big thing.

I get some bean counters may think "we don't want them with 5600x/5800x getting a 5950x for cheap", but that doesn't seem realistic. Those that want maximum performance and guaranteed functionality can by the 5900/5950X and there's clearly a market for this. However, those buying lesser chips with disabled CCD can attempt to unlock it and it comes down to the silicon lottery. Some will get lucky (maybe they get a chip that's CCD was disabled because it couldn't qualify for use under lower but within spec power/mobo etc... conditions, but they're running it on a high end setup and it runs flawlessly once unlocked and given the voltage and cooling it needs) , others will not (either unable to unlock it functionally at all, unlocks but significantly lower clocks/performance etc) but they still get the full features of the chip for which they paid.

Guess we'll see.
 

Azrak

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I wonder if those CPUs with 2 CCDs are indeed failed 5900Xs and 5950Xs that weren't caught in phase-1 validation when the CCDs were not glued to the substrate, but caught in phase-2 testing after the CPUs are fully made. Like maybe some kinds of testing cannot be done at the raw CCD level and must be done after installation onto the substrate and hooked up to the IO die.
 

MavericK

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I would have to think there is *some* impact to this, whether it's perceivable or not, going from one CCD to two seems like it would introduce at least some level of latency within the chip.

I know in my BIOS you are able to make changes per CCD, so I wonder if these would show up differently?
 

Rizen

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I would have to think there is *some* impact to this, whether it's perceivable or not, going from one CCD to two seems like it would introduce at least some level of latency within the chip.

I know in my BIOS you are able to make changes per CCD, so I wonder if these would show up differently?
Well technically they're not going from 1 CCD to 2. The second CCD is fully disabled and all of the utilized cores are on just one CCD. It's physically present, but not used at all, so there should be no latency penalty (which comes from the CCDs having to communicate with each other through Infinity Fabric).
 

MavericK

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Well technically they're not going from 1 CCD to 2. The second CCD is fully disabled and all of the utilized cores are on just one CCD. It's physically present, but not used at all, so there should be no latency penalty (which comes from the CCDs having to communicate with each other through Infinity Fabric).
Gotcha, for some reason I was not clear on that - thanks.
 
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