Do you think we'll see barcelonas with 2 cores disabled?

nonameo

Gawd
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If the cache is good but all 4 cores don't pass stability, you should still be able to utilize the 2mb of shared cache, right? Although, I don't really see much point in pushing a performance dual core processor seeing that the quad core is supposed to be the "performance" part and they'll probably have an independently manufactured dual core processor for all of their dual core CPUs.
 
Kuma is the dual core variant of K8L that includes L3 cache - we'll see it on the desktop a few months after Agena shows up; sometime in Q1 2008 probably.

X2s continue on for a while as budget dual core option after Kuma launches.
 
Kuma is the dual core variant of K8L that includes L3 cache - we'll see it on the desktop a few months after Agena shows up; sometime in Q1 2008 probably.

X2s continue on for a while as budget dual core option after Kuma launches.

Yes, but to my understanding that will be a true dual core die.

What I'm asking is if we'll see 4 core dies with only 2 cores enabled, but full L3 cache.
 
Yes, but to my understanding that will be a true dual core die.

What I'm asking is if we'll see 4 core dies with only 2 cores enabled, but full L3 cache.

The original x2 where a true dual core die only the pentium d's where two single cores glued together.
 
The original x2 where a true dual core die only the pentium d's where two single cores glued together.
Yes, but he wants to know if we'll see a dual-core Barcelona with the full 2MB of L3 cache. He is primarily interested in the cache not the cores.
 
If the cache is good but all 4 cores don't pass stability, you should still be able to utilize the 2mb of shared cache, right? Although, I don't really see much point in pushing a performance dual core processor seeing that the quad core is supposed to be the "performance" part and they'll probably have an independently manufactured dual core processor for all of their dual core CPUs.


I dont see why we would not ! AMD has to do something with the faulty cores.I mean if you make a quadcore but one or two out of the four is suspect,then why not...

Better then just junking them altogether,at least some cash can be made on them.
 
Yes, but he wants to know if we'll see a dual-core Barcelona with the full 2MB of L3 cache. He is primarily interested in the cache not the cores.

Kuma will have 2 MB of L3. L3 is not tied to the number of cores, it's not like there is 512kb of L3 per core for Barcelona, each die has a single bank of L3 cache accessible by all cores.
 
AMD did it with Barton. they just called it Thorton instead. I dont see any reason why they couldnt do the same thing here.
 
Its within the realm of possibility, but my guess is that the single die of barcelona is going to take up alot of space, so if you disable two cores, all the heat is going to be produced unevenly which may be a problem.

I know with intel, they alot of times have chips that work fine, but parts of the L2 cache are fried, so they disable it, and sell them as cheaper celerons or what not, im just wondering if its possible to have two cores fail on a barclona without the L3 cache being effected, and if so how does that L3 compensate for two less cores (being shared).
 
Its within the realm of possibility, but my guess is that the single die of barcelona is going to take up alot of space, so if you disable two cores, all the heat is going to be produced unevenly which may be a problem.

Power distribution is very uneven across dies already, active logic uses about 10 times the power per unit area as SRAM does.

I know with intel, they alot of times have chips that work fine, but parts of the L2 cache are fried, so they disable it, and sell them as cheaper celerons or what not, im just wondering if its possible to have two cores fail on a barclona without the L3 cache being effected, and if so how does that L3 compensate for two less cores (being shared).

L3 doesn't care how many cores there are.
For performance reasons, L3 is most effective with multiple cores because one of its primary functions is to hold a clean copy of a data object being used by two or more cores. In the current X2s there is no shared memory on die so to preserve the integrity of data, changes must be written back to main memory before ownership is changed between cores. K8L will allow those updates happen in L3 on the die. When core needs to write to data that is loaded by multiple cores, the data is locked in L3, the changes are made and written back to L3 and the data is unlocked for the other cores.

But even in a single core application, L3 serves some use since it is an exclusive cache - when a line is evicted from private L2 cache, it may be placed in L3 if L3's replacement algorithm finds a line in the shared cache that should be evicted to make room for the data removed from L2.
 
Maybe, if there are enough of them, I have not heard anything about Dual Core Opteron based on K10 technology so far, it's all been about Barcelona's native Quad Core.

Though it's easily within the realm of possibility, as AMD made Manchester based Athlon 64's with one defective core disabled.
 
Though it's easily within the realm of possibility, as AMD made Manchester based Athlon 64's with one defective core disabled.

Really? Interesting. In that case I'd bet they probably would turn quads into duals at some point. Probably wouldn't keep all the cache though, sheerly so as to conceal what the chip really is.
 
Yes, but he wants to know if we'll see a dual-core Barcelona with the full 2MB of L3 cache. He is primarily interested in the cache not the cores.

yes, a quick glance at the die plot clearly shows that disabling cores has nothing to do with how much L3 is available
 
yes, a quick glance at the die plot clearly shows that disabling cores has nothing to do with how much L3 is available
Why address this reply to my post?? Quote the poster who requires this information, otherwise it may go unnoticed. ;)
 
it would make economical sense, but they'd have to design that into the arch. They might not have even considered that, thinking that their 65nm process was going to be great. GPU makers do it with fuses built in that they can laser off. I don't think it would cause uneven heating/hotspots that couldn't be taken care of, they are pumping out less heat. The problem may lie with the memory controller and the dual 64 bit channels. They haven't given us enough info on it. I'd honestly think they'd just go with the quads and set the center bin a lot lower until they figure out the process while producing native dual cores as well. We'd have to see all the data to see which choice would be preferable, but alas, AMD is an impenetrable fortress which leaks no info.
 
Why address this reply to my post?? Quote the poster who requires this information, otherwise it may go unnoticed. ;)

cause you posed the question in an elegant fashion, it was easier to answer :D
 
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