Design Leak: 72 Zeus Cores, 4x HBM2E, 4-6 DDR5

[erek]

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"In a close-up and up-scaling of the image, we can see that it’s a detailed floor-plan of the server SoC Rhea, labelled for a target TSMC 7nm process.

We can detail 72 CPU cores and 68 mesh network L3 cache slices in the floor plan, surrounded by various IP whose labels are too small to be legible. SiPearl had previously confirmed that the project uses Arm’s upcoming Neoverse “Zeus” cores which succeed the Neoverse N1 Ares cores that are being used in current generation Arm server SoC designs such as Amazon’s Graviton2 or Ampere’s Altra.

Beyond the confirmation of a core-count, we also see that the Rhea design sports a high-end memory subsystem, with the floor plan labelled as having 4x HBM2E controllers and 4-6 DDR5 controllers. Such a hybrid memory system would allow for extremely high bandwidth to be able to feed such a large number of cores, while still falling back to regular DIMMs to be able to scale in memory capacity."

https://www.anandtech.com/show/16072/sipearl-lets-rhea-design-leak-72x-zeus-cores-4x-hbm2e-46-ddr5

 

[juanrga]

 

[defaultluser]

I knew this was coming, after the success of N1. It's likely the server version of Hercules , AKA A78 (hence the same Greek gods namespace).\

I'm assuming the market name will be the Neoverse N2?