"No, AMD Infinity Cache Isn’t for RDNA 2 GPUs: It’s for Die-to-Die Interconnects" ~ says Areej of hardware times.
https://www.hardwaretimes.com/no-am...-interconnects/amp/?__twitter_impression=true
today an AMD patent has surfaced that describes what Infinity Cache really is. The important lines from the patent are as follows:
https://t.co/acLPZhsmpR?amp=1
https://www.hardwaretimes.com/no-am...-interconnects/amp/?__twitter_impression=true
today an AMD patent has surfaced that describes what Infinity Cache really is. The important lines from the patent are as follows:
The Infinity Cache will be used in SoCs, namely designs with a CPU, GPU, and DRAM on the same package. The Infinity Cache will be used to improve the latency between the various dies, chips, and sockets. This makes it clear that IF won’t be used on any Navi 2x GPU including Big Navi as it’s a single-chip solution. Future GPUs with a chiplet (MCM) design, may, however, see the use of this cache to reduce the latency penalty between the various GPU dies.System-on-chip (SoC) architecture for use with central processing units (CPU) and graphics processing units (GPU), namely, SoC architecture that connects die-to-die, chip-to-chip, and socket-to-socket, used across different microprocessors to enable increased computing performance; network-on-chip, namely, technology that provides interfaces across microprocessor CPU and GPU cores, memory, hubs, and data fabric to enable microprocessor communications and increase computing performance and efficiency; microprocessor communication fabric, namely, data communication interconnect architecture responsible for collecting data, and command control interconnect architecture responsible for data sensor telemetry
AMD Patent
https://t.co/acLPZhsmpR?amp=1