Cerebras’ wafer-size chip is 10,000 times faster than a GPU

erek

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"Depending on workload, from AI to HPC, the CS-1 delivers hundreds or thousands of times more compute than legacy alternatives, and it does so at a fraction of the power draw and space.

Feldman noted that the CS-1 can finish calculations faster than real time, meaning it can start the simulation of a power plant’s reaction core when the reaction starts and finish the simulation before the reaction ends.

“These dynamic modeling problems have an interesting characteristic,” Feldman said. “They scale poorly across CPU and GPU cores. In the language of the computational scientist, they do not exhibit ‘strong scaling.’ This means that beyond a certain point, adding more processors to a supercomputer does not yield additional performance gains.”

Cerebras has raised $450 million and has 275 employees."


https://venturebeat.com/2020/11/17/cerebras-wafer-size-chip-is-10000-times-faster-than-a-gpu/amp/
 
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46,225mm^2 huh? I wonder what kind of yield they get out of those puppies :p


My God,it can't be great. This article/press release sounds alot like Quantum Computing/aka snake oil the CIA's of the world will throw untold billions of taxpayer money into.
 

UltraTaco

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Just for laymen like taco, here is conversion:

Screenshot_20201118-201613_Opera.jpg


If you have 12x12 floor tiles in your house, it's about half a tile.:)
 

DPI

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If it can mine 1 Bitcoin per second I wouldn't necessarily line up outside of Microcenter at 6AM for it but I might roll in by 6:45.
 

Red Falcon

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I would say Skynet, but even Skynet was only capable of 90 TFLOPS.
Wow, these are the types of chips that will power rouge AI consciousnesses like those found in the Renraku Archology... :borg:

cerebras-2.jpg
 
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cdabc123

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I wonder what node they use to achieve yields good enough to make a chip this size viable
 

ChadD

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I wonder what node they use to achieve yields good enough to make a chip this size viable
For the cost of the machines its going in.... they can probably afford to toss 50 wafers to get one working chip. lol

In all seriousness though for the application they are talking about IF... their claims are possible. One chip could replace 100s perhaps 1000s of regular Power or x86 chips. Which might make a terrible yield feasible. Also all the savings on interconnects tech ect.
 

cdabc123

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For the cost of the machines its going in.... they can probably afford to toss 50 wafers to get one working chip. lol

In all seriousness though for the application they are talking about IF... their claims are possible. One chip could replace 100s perhaps 1000s of regular Power or x86 chips. Which might make a terrible yield feasible. Also all the savings on interconnects tech ect.
Eh... Its a asic printed on a whole wafer. I'm going to assuming they are using a larger node as anything cutting edge would make such a chip impractical. I dont believe marketing pitch however would love to see the benefits of a full wafer asic.
 
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serpretetsky

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older aticle:
https://spectrum.ieee.org/semicondu...-chip-will-smash-deep-learnings-speed-barrier

tidbits I found interesting:

defects:
it was possible to fit in enough redundant cores to account for the defect-induced failure of even 1 percent of them and still have a very powerful, very large chip.

layout:
The big challenge was finding a way to link those pseudochips together. Chipmakers leave narrow edges of blank silicon called scribe lines around each chip. The wafer is typically diced up along those lines. Cerebras worked with Taiwan Semiconductor Manufacturing Co. (TSMC) to develop a way to build interconnects across the scribe lines so that the cores in each pseudochip could communicate.

voltage and power:
The WSE’s 1.2 trillion transistors are designed to operate at about 0.8 volts, pretty standard for a processor. There are so many of them, though, that in all they need 20,000 amperes of current. “Getting 20,000 amps into the wafer without significant voltage drop is quite an engineering challenge—much harder than cooling it or addressing the yield problems,” says Lauterbach.

Power can’t be delivered from the edge of the WSE, because the resistance in the interconnects would drop the voltage to zero long before it reached the middle of the chip. The answer was to deliver it vertically from above.

thermal expansion:
“The challenge of [coefficient of thermal expansion] mismatch with the motherboard was a brutal problem,” says Lauterbach. Cerebras searched for a material with the right intermediate coefficient of thermal expansion, something between those of silicon and fiberglass. Only that would keep the million power-delivery posts connected. But in the end, the engineers had to invent one themselves, an endeavor that took a year and a half to accomplish.
 

serpretetsky

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That’s a humongous CPU. Perfect time to resurrect this thread!
I see a lot of posts in this thread and that old thread talking about how this chip is probably very difficult to produce because of poor yields and an enormous chip area. While I'm sure it is difficult, I'm not sure it's as bad as finding a defect and throwing the whole wafer out.

Regular chips are already binned and entire portions of them deactivated when defects are found. The chip is still used in a product, but instead of 8-core cpu we end up with a 6-core cpu with 2 deactived cores. Take the same idea and scale it up one more step.

They discuss how really the cerebras is a bunch of individual logical chips on a single wafer (the same way you would produce any chip), and that in terms of logic layout the only special thing is that interchip communication between the logical chips is handled on the same silicon instead of routed through PCB.

So make sure you can bin each logical chip (including deactivating the entire logical chip if you need to), and make sure the interchip communication will not fail for small defects. You could, for example, layout the interchip communication to be much larger than typical, like use 180nm rules. I'm assuming the interchip communication is done on higher level larger metal layers anyways, I'm not sure how commonly those layers get defects. Or perhaps you can design in some other redundancy systems that will allow one part of the intercommunication busses to fail but for the system to keep working anyways.
 

Brian912

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Now were talking, I can finally cook a mean sunny side up with this thermal footprint.
 

mashie

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