Cascade Lake-X Pricing and Model List

Sycraft

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TR3 should fair better with gaming this time around as it does not use NUMA, which the Windows scheduler has struggled with. So a game mode will probably not be necessary like past TR chips. I would expect similar boost frequencies as in Ryzen, probably will need some serious cooling to maintain higher clocks given how many cores these are expected to have though.
I wonder if that is actually the Windows scheduler, or a combination of it and how AMD implemented NUMA. Reason I wonder is in multi-socket systems, which we use at work all the time, it has no issues with NUMA. In fact in things like Hyper-V you can tell it if a VM is allowed to span NUMA nodes or not, and in general it'll group threads from a process on a single node when it can. So I wonder if the issue was that the chips weren't properly exposing their NUMA topology to Windows so it can't tell which core is associated with which node, and thus do proper scheduling.

Either way if they don't use it on their new chips then it is problem solved and life is good :D.
 

Ebernanut

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I would take SL stats with a grain of salt. Their business model is to sell bin chips. It seem it is a lot more common to hit 5Ghz based of what I seen on forums.
Their numbers are definitely skewed because they don't take the time to properly dial in overclocks and likely hedge the rating some so it can still be achieved on slightly substandard hardware. And you're right that it's self serving for them to publish the skewed numbers but I would also take feedback in forums with a grain of salt since IME people are much more likely to mention positive results when it comes to overclocking.

Reality is likely somewhere in the middle.
 

1_rick

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And to top it all off, these numbers given as the "process size" are not at all in relation to "transistor size"
The way I remember it is that "7nm" or whatever is the thickness of a trace (it's a bit more specific than that but I don't remember exactly what), not the size of any given component. So 7nm or 10nm or whatever isn't transistor size at all, and apparently there's still variances between processes in spacing and the like, which is why they say Intel's 10nm is similar to TSMC's 7nm, as it's got slightly denser transistors or something. (Or, it used to, but marketing has kind of thrown that out.)

I did a quick bit of searching and this seems like a pretty good short introduction: https://en.wikichip.org/wiki/technology_node
 

Uvaman2

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All they are doing is OEM princing for all. Perhaps is still higher anyway.
 

Armenius

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The way I remember it is that "7nm" or whatever is the thickness of a trace (it's a bit more specific than that but I don't remember exactly what), not the size of any given component. So 7nm or 10nm or whatever isn't transistor size at all, and apparently there's still variances between processes in spacing and the like, which is why they say Intel's 10nm is similar to TSMC's 7nm, as it's got slightly denser transistors or something. (Or, it used to, but marketing has kind of thrown that out.)

I did a quick bit of searching and this seems like a pretty good short introduction: https://en.wikichip.org/wiki/technology_node
Had a short discussion on this in the GloFo thread, but the node is the space between the gates. Intel's process is still "winning" because they are using a half-pitch closest to what they advertise, so their transistor density has always rivaled process nodes from TSMC that are advertised to be tighter. Could be why Intel has been having issues with 10nm because EUV introduced new issues that need to be dealt with like shot noise if they want to keep the half-pitch close to what they promised and designed.
 

Snowdog

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The way I remember it is that "7nm" or whatever is the thickness of a trace (it's a bit more specific than that but I don't remember exactly what), not the size of any given component. So 7nm or 10nm or whatever isn't transistor size at all, and apparently there's still variances between processes in spacing and the like, which is why they say Intel's 10nm is similar to TSMC's 7nm, as it's got slightly denser transistors or something. (Or, it used to, but marketing has kind of thrown that out.)
There is no real connection to any real physical dimension any more. It's a marketing name and nothing more.

You can look real measurements like transistors/mm2. For instance.

NVidia 10 series GPU on TSMC 16nm = ~25million transistors/mm2.
NVidia 20 series GPU on TSMC 12nm = ~25million transistors/mm2.

Note that reported node size change, but there was zero change in transistor density. IOW it's marketing, not real dimensional measurements.

AMD GPU on TSMC 7nm = ~40million transistors/mm2. So a real change, but it is NOT double the density of TSMCs previous 16nm/12nm process.
 

MMitch

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There is no real connection to any real physical dimension any more. It's a marketing name and nothing more.

You can look real measurements like transistors/mm2. For instance.

NVidia 10 series GPU on TSMC 16nm = ~25million transistors/mm2.
NVidia 20 series GPU on TSMC 12nm = ~25million transistors/mm2.

Note that reported node size change, but there was zero change in transistor density. IOW it's marketing, not real dimensional measurements.

AMD GPU on TSMC 7nm = ~40million transistors/mm2. So a real change, but it is NOT double the density of TSMCs previous 16nm/12nm process.
You may want to take a market with competition to actually make an argument and not compare monopoly at bleeding edge....
Edit: I might have understood it the wrong way :) I agree with you, numbers are marketing but actual results are stories...
 
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Sycraft

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You may want to take a market with competition to actually make an argument and not compare monopoly at bleeding edge....
Edit: I might have understood it the wrong way :) I agree with you, numbers are marketing but actual results are stories...
No it is a pretty good demonstration. We are talking the same fab, but a new process. Had the process really shrunk in the way 16nm-12nm would imply, you'd get a lot more transistors per mm. However you don't which means things really didn't get any smaller, it is just a marketing number.
 

GoodBoy

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There is no real connection to any real physical dimension any more. It's a marketing name and nothing more.

You can look real measurements like transistors/mm2. For instance.

NVidia 10 series GPU on TSMC 16nm = ~25million transistors/mm2.
NVidia 20 series GPU on TSMC 12nm = ~25million transistors/mm2.

Note that reported node size change, but there was zero change in transistor density. IOW it's marketing, not real dimensional measurements.

AMD GPU on TSMC 7nm = ~40million transistors/mm2. So a real change, but it is NOT double the density of TSMCs previous 16nm/12nm process.
Yeah, I found the same thing.

Chances are something about the process did change/improve, but the density wasn't it.
 

Armenius

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Yeah, I found the same thing.

Chances are something about the process did change/improve, but the density wasn't it.
The MMP was slightly improved on their 12nm process, but that was about it. It looks like it wasn't enough to affect density in any significant way. It supposedly maximizes the 16nm process by minimizing leakage, but was probably more about reducing cost as much as possible.
 

GoodBoy

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Well if they can reduce gate leakage, that will lower temps, and probably increase clocks.
 
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