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Very true, but Like mpcamer1220 said, I would expect AMD having more reason to do this because of their single chip quad-core design. Intel would likely just disable their second chip altogether if there's one bad core. If AMD does indeed go forward with this, it would make for a very interesting product, that's certain.
That's the reason I don't buy the rumor until I read it from someone else. The Inq states that AMD will be doing this but not because of bad yields. They make it appear as if it's a marketing innovation. Maybe yes, maybe no, I don't know, but if they are getting a significant number of bad yields, why not sell them off at a lower price to make some needed profit? Heck, I would probably do the same in their position.
Definitely. There's always a buyer for almost every product. I don't think finding a buyer for a new tri-core processor is the biggest concern if it's primarily a salvage scenario.
That ultimately would depend on the planned price point, and what the competitive landscape appears like at that hypothetical juncture. Moreover, a tri-core processor will permit AMD's OEM partners to market systems at additional price brackets, not to mention increased product differentiation within their respective product stables. Even if we are talking negligible performance difference between dual/quad cores, the average consumer will just equate 3>2 performance, but 3<4$.
You mean Fusion?
This is clearly AMD spinning a story.
Yeah, Intel would never market a partially defective processor at a lower price point. *COUGH*Celeron*COUGH*Pentium T Series*COUGH*
True, true... how soon we forget!Yeah, Intel would never market a partially defective processor at a lower price point. *COUGH*Celeron*COUGH*Pentium T Series*COUGH*
The MCM design has both advantages and disadvantages, as does a single chip design.
Good question, I believe the memory controller was divided in two to access both memory channels independently of each other, thus data can flow to and from both memory channels simultaneously. If that's the case, then the individual memory controllers should have access to all cores, but this is pure speculation on my part, so don't quote me on this.
Which means another escalation in the price war and better for the consumer.
The MCM design has both advantages and disadvantages, as does a single chip design.
Good question, I believe the memory controller was divided in two to access both memory channels independently of each other, thus data can flow to and from both memory channels simultaneously. If that's the case, then the individual memory controllers should have access to all cores, but this is pure speculation on my part, so don't quote me on this.
Which means another escalation in the price war and better for the consumer.
I don't think that having separately clocked cores will work correctly on an SMP system
After all, I can only imagine that it's called symmetric multi processing for a reason.