AMD shows off 3.0 GHz Barcelona with 3x2900 XT?

Assuming there is a new instruction set for either Barcelona or some future revision/generation, won't software require a code update to take advantage of it? That is the case for SSE4 and the previous new Intel instruction sets, AFAIR.
 
APOLLO said:
Assuming there is a new instruction set for either Barcelona or some future revision/generation, won't software require a code update to take advantage of it? That is the case for SSE4 and the previous new Intel instruction sets, AFAIR.
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Yes of course.... It is new instruction in the ISA... They will require software support for them to work. Some instructions can be drop in replacements for others, and can be supported with a simple recompile, other instructions dont have any past precedence and will need OS support at the minimum, and application support at the most.
 
There are a few sites that are saying a 3.0ghz Phenom has cracked 30,000 3DMark06 points.
http://theinquirer.net/?article=41970

I'm not too sure if this is correct. Apparently to get a score this high you would need ~21,000 cpu points. Clovertown at 5ghz gives ~7000 points.

Could this be the new instuctions at work?
Doubtful I think, but possible....

Bring on September 10.
 
Could this be using that reverse hyperthreading thing they were talking about a while back? If I recall correctly it was to use multiple cores to execute a single thread. Maybe they got it working?
 
BigDH01 said:
Won't be seen in Barcelona.
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I don't like to assume anything, as should you, or Arstechnica. (because assuming makes an ass outta you and me ;) ) Personally, I'll wait and see what AMD has to say about the matter come it's release thanks. No one knows definitely what all features are coming with Barcelona/K10's release.(except maybe Morfinx haha :D Damn NDAs! )
 
Lou Ceifer said:
I don't like to assume anything, as should you, or Arstechnica. (because assuming makes an ass outta you and me ;) ) Personally, I'll wait and see what AMD has to say about the matter come it's release thanks. No one knows definitely what all features are coming with Barcelona/K10's release.(except maybe Morfinx haha :D Damn NDAs! )
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Yeah, I'm sure a proposal that was set forth on August 16th will make it into a CPU that should've already been shipping at that time. It's not about assuming, it's about the fact that a proposed standard won't be implemented in a chip who's design is already complete and who's die is already being fabricated.
 
BigDH01 said:
Yeah, I'm sure a proposal that was set forth on August 16th will make it into a CPU that should've already been shipping at that time. It's not about assuming, it's about the fact that a proposed standard won't be implemented in a chip who's design is already complete and who's die is already being fabricated.
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This has been talked about for a long time now and being an instruction set it can be added at any time. I would be surprised if it would go into Barcelona now but it's certainly possible for Phenom and it also would explain the 30,000 3DMark 06 score.
But still it's an assumption. And it's starting to make me itchy.:)
 
as355 said:
This has been talked about for a long time now and being an instruction set it can be added at any time. I would be surprised if it would go into Barcelona now but it's certainly possible for Phenom and it also would explain the 30,000 3DMark 06 score.
But still it's an assumption. And it's starting to make me itchy.:)
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I was going to mention the new instruction set as a plausible explanation in the 3DMark thread, but decided not to since my knowledge in this area is rather limited. Do you think that could be a possible explanation for the high score, if indeed true? Wouldn't that imply the use of an optimized benchmark, though?
 
as355 said:
This has been talked about for a long time now and being an instruction set it can be added at any time. I would be surprised if it would go into Barcelona now but it's certainly possible for Phenom and it also would explain the 30,000 3DMark 06 score.
But still it's an assumption. And it's starting to make me itchy.:)
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Phenom is already in production so the earliest is Shanghai. And nothing will explain that 30k mark at this point and without more information (specifically subscores).
 
APOLLO said:
I was going to mention the new instruction set as a plausible explanation in the 3DMark thread, but decided not to since my knowledge in this area is rather limited. Do you think that could be a possible explanation for the high score, if indeed true? Wouldn't that imply the use of an optimized benchmark, though?
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all that it implies, if true... is that AMD's new architecture is absolutely riveting
 
Leepox said:
all that it implies, if true... is that AMD's new architecture is absolutely riveting
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So not only will it be the fastest thing on the planet, but it will do rivet work too. Man that is just what I need for my case mods!!!

Seriously, I hope that this is true, but lets wait for more proof before we start throwing parties and the inevitable 'I told you so'
 
BigDH01 said:
Yeah, I'm sure a proposal that was set forth on August 16th will make it into a CPU that should've already been shipping at that time.
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A proposal that was in the works for no telling how many months is more like it. OR perhaps years. AMD developed Intel's x86 into their 32-bit compatible, 64-bit extended x86-64 ISA, and blazed that trail with the Athlon 64 and it's derivatives for the past 4 years of which Intel followed suit with the P4 and Core family. That means since they initially developed it and now it's established in the industry, they are pretty free to modify it from here on out as they see fit as long as it keep it's compatibility, particularly if it's to improve on it, more power to them I say. Intel keeps adding new SSE microcode every generation it seems, why can't AMD start extending additional x86-64 instructions is the way I see it.

Above all, a code change like this in the x86-64 ISA tells me this perhaps is not some fly-by-night idea, as changes in ISA code of this magnitude require YEARS of planning to implement effectively into hardware from what I have seen over the years. Besides, it most likely took AMD 4 years of development with the K8 and the accompanying x86-64 ISA to get it to the market, therefore, it's not so crazy to think that AMD could have already put those extentions in the K10 family, maybe even for use with it's first generation, with Barcelona.

As far as their shipping date goes, it's not like Intel hasn't slipped on their launch dates,(or just flat out paper launched, heh Intel and AMD have both done that in the past) big deal. Nothing is ever set in stone, least of all in the fast moving semi-conductor industry and being on this forum long enough you would know this.

BigDH01 said:
It's not about assuming, it's about the fact that a proposed standard won't be implemented in a chip who's design is already complete and who's die is already being fabricated.
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Haha, this forum is all about ASSuming, who ya kiddin?. Like I said, AMD's been working on this chip for the past 4 years, alot can happen in that kind of time frame, what seems or is reported as a proposed standard to us could very well be something AMD has already been working on in the K10 for the past 2-3 years and are now just documenting it for the programmers. Regardless, we'll find out in coming weeks for sure, until then, knock yourself out believing whatever you like. All will be revealed soon and all speculation put to rest, finally.( which sucks because I'm going on vacation the week Barcelona is released too, with no internet, bummer :( )
 
Unfortunately I've found out it has only been announced.
It won't be available until 2yrs. (Bulldozer)

That should give intel enough time to copy AMD's patents :(
 
Then, the new instruction set is something else entirely or already existing but optimized instructions...?
 
as355 said:
Unfortunately I've found out it has only been announced.
It won't be available until 2yrs. (Bulldozer)

That should give intel enough time to copy AMD's patents :(
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Yep, I read about the SSE5 story this morning. An interesting development to say the least, AMD and Intel do have cross-liscencing agreements on things of this nature, there's no need to copy patents. However, I an curious to whether Intel will (in their eyes) "stoop" to using another AMD created standard, or create something simular like "SSE5a" or "SSE6"?
 
Lou Ceifer said:
Yep, I read about the SSE5 story this morning. An interesting development to say the least, AMD and Intel do have cross-liscencing agreements on things of this nature, there's no need to copy patents. However, I an curious to whether Intel will (in their eyes) "stoop" to using another AMD created standard, or create something simular like "SSE5a" or "SSE6"?
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Or attempt to force software companies not to support SSE5.
If Intel do want to copy them it would be a while. Isn't Nehalem taped out now?

@ APOLLO, I'm not sure what's happening instruction wise now. I was told to keep an eye out for an announcement so I think SSE5 was it.

As for those benchmarks on coolalers site, don't take any notice as they were done with an old B0 heavily patched sample. The retail revisions won't be anything like that chip.
It seems like that guy has the same revision chip that Anand got hold of. If you remember Anand wouldn't publish any results as he rightly believed it was buggy as hell.

Only 5 more days now.:)
 
as355 said:
@ APOLLO, I'm not sure what's happening instruction wise now. I was told to keep an eye out for an announcement so I think SSE5 was it.
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I think so too.

As for those benchmarks on coolalers site, don't take any notice as they were done with an old B0 heavily patched sample. The retail revisions won't be anything like that chip.

It seems like that guy has the same revision chip that Anand got hold of. If you remember Anand wouldn't publish any results as he rightly believed it was buggy as hell.
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Very likely. I'm totally ignoring his 'results' and the B1 samples although representative of release batches, will be eclipsed by the B2 stepping before year's end.

Only 5 more days now.:)
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Maybe a bit sooner according to morfinx.
 
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Cyrilix said:
Well, for the high clockspeed processors, they may just decide to charge something in the range of $1000, and therefore reduce demand.
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Yes, because raising prices to objectively wrong levels is sure to curb demand.......................

this comment aged like an open can of sardines :(
 
pendragon1 said:
and if you think of the 8xxx cjips as what they really are 4 core/8 thread, not full 8 cores they are not so bad.
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Yeah, but they were released at the same time as Sandy Bridge, my i7-3930k is still kicking today as a test box.
 
ND40oz said:
Yeah, but they were released at the same time as Sandy Bridge, my i7-3930k is still kicking today as a test box.
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and i have a 8350 "test box"...
edit: the i7 was also twice the price...
 
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pendragon1 said:
and i have a 8350 "test box"...
edit: the i7 was also twice the price...
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between AMDs odd marketing, Tech review sites not reviewing them in a 'like price' model, constant mainstream negative press, battling lawsuits for and against AMD, it is amazing AMD ever made it out, let alone actually made a run for the lead.

the number of times I heard 'tech people' say 'You are building an AMD computer? why? they suck.' with no actual knowledge other than a reference to a single Tom's Hardware article....
 
pendragon1 said:
and i have a 8350 "test box"...
edit: the i7 was also twice the price...
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By test box, I mean I just retired it as my main workstation when I got a i7-12700k two months ago. Getting 10 years out of a daily driver was pretty unbelievable, just did video card upgrades over the years ending with a RTX 2070S. The final straw was not being able to find a tpm chip for the X79 board.
 
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