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Let's review your question exactly as you put it.
That's so damn general you could drive a bus through it.
And I'm just going to tell you that you are trying to be facetious but don't know how to do it correctly, or were you being dishonest when you knew an answer? Essentially you are being too cute by half and hoping no one realizes it. What you are attempting to argue is that IPC is a strictly defined definition to mean only one thing and one thing only (max throughput and in your case any instruction type). This is not the case from a programmatic point of view, or real world workloads (this right here is why we test with them to begin with).
Sure in a perfect world ( I seem to remember it being 4 though). If you were correct with your assertion with regards to software then no matter what compiler tuning was given upon compile we would always get the same result. We don't not even close. You are attempting to conflate IPC from max throughput of an architecture, and then go on to claim that it can be universally applied to every workload without taking into account, branch mispredicts, pipeline stalls, latency, bitness, or cache size. Sure it's 8 instructions per cycle but it isn't with shitty code, or code meant for another architecture. This is just not going to fly with anyone. I mean it's kind of cute, but demonstrably ignorant. The whole point of providing you with that link is to show that actual software that people use can affect any architecture's capability to achieve max throughput, especially when it came to BD.
No one believes that except you...like literally. Any chip without software is a paper weight. It's not processing a damn thing without it, nor will it understand how to process it without it.
This much is very true. But that's not what you are arguing here. You also fail to realize that shitty code can have implications regardless of what should be possible.
Vague, but I thought you didn't know at all?
Ignorance is bliss as they say. However, you might want to read some in depth analysis of any CPU architecture because all of it reviews max throughput against all of the different scenarios I listed above. It would do you some good that way when you figure you are going to be too cute by half with anyone maybe just maybe you will think twice.
Its not me trying to credit it all on 1 person. Whatever it ends as a success or not have nothing to do with Keller.
So now he is the chief architect, lead designer. What else?
Heh...
I'm just going to tell you up front you have no idea what you are talking about. IPC (or MIPS) are absolute. It was a rhetorical question because people throw around IPC without knowing what it is.
But in cause you are wondering, Bulldozer's integer instructions per clock cycle is 8.
Which means it's MIPS (per core) is 8 * <MHZ Clock>
What software is involved is meaningless. This is a hardware specification which has software *implications*.
"Ricin" on the other hand has 16 instructions per clock cycle. Like the Intel chip used in the AMD demo.
All you had to do was know what you were talking about- no Google needed
Other factors also affects the outcome of this render - as in render resolution. AMD should just be very clear on what settings (all of them) used. Such as default but samples 150 etc. It could have been samples 100 and resolution of 1024x768 vice 800x600.
Now by the way, am I the only one here that gets turned on by Su???
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Look, I am not a fan of AMD. I have not been for at least 10 years. But, I do understand trends and history repeating. If you knew the history of AMD you would realize great progress occurred each time Jim Keller was involved. Despite your constant denial, Jim Keller -was- involved in the development of the K7 processor, on a -team-, and he -was- Lead Architect of the K8 microarchitecture. Initial K8 design was canceled, with Fred Weber taking over and running with K7 design revised into a 64-bit core. Again, Jim Keller -was- involved in the development of the HyperTransport specification and x86-64 instruction set (again through -teamwork-, as he was not the only author: Dirk Meyer, Fred Weber, Kevin McGrath and others were involved). Jim Keller -was- hired as Chief Architect to completely restructure their roadmap which led to the design of Zen architecture. To deny his involvement in the formation and development of Zen project would be sheer ignorance.Its not me trying to credit it all on 1 person. Whatever it ends as a success or not have nothing to do with Keller.
So now he is the chief architect, lead designer. What else?
From arguing about benchmark percentages to arguing if the guy who AMD said worked on the chip actually worked on the chip, bravo thread bravo
Are you sure about that? Just for reference, this was one of the articles I was looking at. https://people.cs.clemson.edu/~mark/architects.html
The P3 came out 2 years after the K6 and a few months after K6-III. Are you confusing the socket versus the chip? There were some really big differences between K6-III vs P3. First the FPU on the P3 was almost twice as fast the cache also was leagues quicker than what was in the K6-3. Now the branch prediction units on the K6 family were leagues better than what the P3 had and I seem to remember the power usage of K6 to be a lot higher than on P3.
