AMD launches Ryzen Mobile 7 2700U & 5 2500U with Vega Graphics

[IdiotInCharge]

I'm actually excited about it, to the degree that APUs make sense.

I don't really have a personal use for one, but I can certainly see the uses, and AMD has shown the potential to offer a different mix of mobile performance without notable compromise. We'll see if they can live up to that potential!

 

[sirmonkey1985]

It seems like people don't like the idea of AMD doing well, the hoops that were jumped through to defend a paper launch and spending 2.5x the MRSP price and the other shortcomings but if AMD produces what appears to be a very good ultrabook part, it is like everyone loses their shit.

yup i know what you mean.. been like that for years on most of the popular forums.

 

[juanrga]

BS and my god a lot of it. That is not how it works. IPC is determined by instructions per clock. IPC is then a function of code so any execution units available are because the code did not make use of them. You also have to add cache and front end mechanics ie: Instruction set decode and saving. That is why AMDs implementation curb stomps Intels. You need to read up.

IPC is Instruction Per Cycle, and yes it depends on the code. The above diagram is a simplification representing only average IPC.

The reason why AMD's implementation of SMT produces higher gains with a second thread is because the Zen microarchitecture is more distributed and unable to extract enough ILP from a single thread to fill all the execution units. It is also the reason why Intel has much higher IPC.

Maybe you would would revise the goal of SMT and why it was invented.

Of course not, i only believe intel slides and leaks

No one said you to believe that. What was said to you was expect to third-party reviews.

He was calling BS on Juangra saying Intel and AMDs implementation of SMT is equally effective.

He didn't understand what I said, neither you do.

Wrong, Zen core has a wider execution pipeline. It can decode 6 instructions at once while Skylake/KL/CL can only do 4.

Wrong. Zen only can decode up to 4 instructions per cycle.

Zen is 6-wide issue. Haswell and above are 8-wide issue.

 

[IdiotInCharge]

yup i know what you mean.. been like that for years on most of the popular forums.

To be fair to the skeptics, AMD has certainly earned the skepticism. They had their ups and they had their downs, and they had their 'almosts'; we know Ryzen is doing pretty well as is Vega, in architecture terms, but every market they introduce it to they're going to have to earn their support.

Don't worry about those that are skeptical before real numbers come in, because that's actually logical.

 

[schmide]

IPC is Instruction Per Cycle,

(snip)


Wrong. Zen only can decode up to 4 instructions per cycle.

Zen is 6-wide issue. Haswell and above are 8-wide issue.

Way to convolve things. Decode and issue are two different things. Haswell+ and Zen can only decode 4 IPC. Zen fuses conditional and jump into one micro-op allowing a theoretical 6-instruction execution. It has been seen to be effective in small loops to 5 IPC.

see here

The long and short of it is. Intel will win heavy AVX and FMA 2-1 (cache and memory aside). AMD will execute tight loops 20-33% faster.

IPC is only as good as the memory system can support it. Intel is still much better at retiring to memory than AMD, thus their SIMD advantage.

 

[reb00tin]

I can't wait to see mini ITX mobos for the 2700U. Looks better than both my i7-6700 and i7-7700 APUs, I can see Intel losing market share to AMD big time.

 

[sirmonkey1985]

I can't wait to see mini ITX mobos for the 2700U. Looks better than both my i7-6700 and i7-7700 APUs, I can see Intel losing market share to AMD big time.

the asrock x370/b250 itx boards looks like good options since they have dual HDMI support. hopefully we start seeing more itx boards though.

 

[NKD]

wonder if apple might go this route with vega apu and quad core ryzen in some of their macbooks in the future. They absolutely try to go decent on gpu given productivity scenario they brag about. I think this should do better than having a dedicated radeon chip. But we do know apple does low ball though so less margins for amd but may help a little with market share.

 

[IdiotInCharge]

wonder if apple might go this route with vega apu and quad core ryzen in some of their macbooks in the future. They absolutely try to go decent on gpu given productivity scenario they brag about. I think this should do better than having a dedicated radeon chip. But we do know apple does low ball though so less margins for amd but may help a little with market share.

The potential is always there; Apple isn't married to Intel except through necessity. If AMD can deliver enough CPU and plenty more GPU, while not just keeping efficiency but also realized battery life under use high, they'll likely find a customer with Apple.

[And Apple is already partial to AMD's GPU architecture with their focus on OpenCL performance (by necessity) and their inclusion of more compute resources across their lineup]

 

[juanrga]

Way to convolve things. Decode and issue are two different things.

Why do you believe I stated that Zen is 6-wide issue but only 4-wide decode?

IPC is only as good as the memory system can support it. Intel is still much better at retiring to memory than AMD, thus their SIMD advantage.

The definition of IPC already includes the memory subsystem.

Intel's SIMD advantage comes from bandwidth. Latest Intel cores have SIMD units that are 2--4x wider than SIMD units on Zen cores. Those wider SIMD units need more bandwidth and so the cache/memory subsystems (and related subsystems) are desinged to provide the needed bandwidth.

Intel also has IPC advantage coming from a better microarchitecture. Zen is more distributed and focused to throughput. Intel is more centralized and focused to latency.

 

[schmide]

Why do you believe I stated that Zen is 6-wide issue but only 4-wide decode?

If you were honestly informing people, you would have stated both Haswell+ and Zen decode as well as issue. Zen 4 decode 6 issue. Haswell+ 4 decode 8 issue. Instead you ignore the fact that Haswell+ is equal to Zen in decode because bigger numbers are big.

muxr was partially right, he or she just didn't explain it well. Zen can do 6 (5) but it has to come from the MicroOpCache.

The definition of IPC already includes the memory subsystem.

Intel's SIMD advantage comes from bandwidth. Latest Intel cores have SIMD units that are 2--4x wider than SIMD units on Zen cores. Those wider SIMD units need more bandwidth and so the cache/memory subsystems (and related subsystems) are desinged to provide the needed bandwidth.

I would actually reverse this. SIMD advantages are actually limited by bandwidth. Just because they are wider doesn't mean they perform better in all cases. They receive some improvement from this, but it is far from optimal.

Intel also has IPC advantage coming from a better microarchitecture. Zen is more distributed and focused to throughput. Intel is more centralized and focused to latency.

What a blind statement. You say one is better then contradict that by touting how Zen has some advantages while Intel has others. Your judgement seems quite clouded.

While many believe that Ray Tracing would be a FP intensive task, it is actually a lot of housekeeping. Those tight loops where Zen accels, must be an advantage somehow for it to perform so well with as you say such a lesser FP system.

 

[DTN107]

I wonder what are the chances of seeing this in Dell Latitudes. Not some new water-down latitude but real latitude notebooks.

 

[jeremyshaw]

I wonder what are the chances of seeing this in Dell Latitudes. Not some new water-down latitude but real latitude notebooks.

The watered down latitudes have made it all the way to the 7000 series. There is no hope, IMO.

 

[N4CR]

Also, what happened to Shintai?

The two intel share shills now only post in the 8th gen thread, as to not create debate in the obsolete z370-390 chipset threads or any non-negative to AMD threads. Eg boosting that thread in search results here.
The other thing they failed at was the leaked RR threads when the other results shitting on intel (which turned out to be accurate) came out.

So with AMD competing with a newer intel CPU and smashing them in mobile, they keep to the only playing ground they have.... 480p 1000hz desktop niche lol.
The shitting on epyc also failed as they are now being deployed in large data centres contrary to the 'they are useless' claims.

 

[juanrga]

If you were honestly informing people, you would of stated both Haswell+ and Zen decode as well as issue. Zen 4 decode 6 issue. Haswell+ 4 decode 8 issue. Instead you ignore the fact that Haswell+ is equal to Zen in decode because bigger numbers are big.

muxr was partially right, he or she just didn't explain it well. Zen can do 6 (5) but it has to come from the MicroOpCache.

Your second post and you already start insulting people...

As many others, I prefer the issue wide to characterize the wide of a core. Why don't I use decode wide? First, because oversizing the front-end is a common technique. A decode wider than the optimal size is part of the arsenal of techniques used to reduce the time needed to achieve steady-state execution in a pipeline after this has been drained. Second, not all the input ISA are equivalent. Indeed 4-wide decode in ARM64 is not the same than 4-wide decode in x64, because one is RISC the other is CISC.

Thus Zen is 6-wide and Haswell and above are 8-wide. And the ratio 8/6 is very close to the 20--30% IPC gap between both.

muxr was wrong. He wrote Zen could decode 6 instructions at once. He was wrong because Zen only can decode a maximum of four instructions.

What a blind statement. You say one is better then contradict that by touting how Zen has some advantages while Intel has others. Your judgement seems quite clouded.

While many believe that Ray Tracing would be a FP intensive task, it is actually a lot of housekeeping. Those tight loops where Zen accels, must be an advantage somehow for it to perform so well with as you say such a lesser FP system.

Before launch, I predicted that Zen would shine in throughput workloads, whereas would fail in latency workloads. Time and reviews have given me the reason.

You seem to believe that latency and throughput have the same importance for a CPU, but it isn't true. Even AMD in its HSA specification acknowledge the existence of two classes of compute units: LCU and TCU.

LCU = Latency Compute Unit. CPUs are instances of LCUs.
TCU = Throughput Compute Unit. GPUs and other accelerators are instances of TCUs.

So the key parameter for a CPU is latency and Zen is lacking in this. AMD has tried to solve this deficiency, first developing a new AGESA version with a ~6ns latency reduction, and latter developing new AGESA versions, as the recent 1.0.0.6, with improved support for faster overclocked RAM. Overclocking RAM somewhat alleviates (hides) the latency problem in Zen.

AMD has designed a CPU that shines in throughput tasks that run better in other chips such as GPUs. Tasks such as rendering and encoding.

 

[Nightfire]

The two intel share shills now only post in the 8th gen thread, as to not create debate in the obsolete z370-390 chipset threads or any non-negative to AMD threads. Eg boosting that thread in search results here.
The other thing they failed at was the leaked RR threads when the other results shitting on intel (which turned out to be accurate) came out.

So with AMD competing with a newer intel CPU and smashing them in mobile, they keep to the only playing ground they have.... 480p 1000hz desktop niche lol.
The shitting on epyc also failed as they are now being deployed in large data centres contrary to the 'they are useless' claims.

Areas of Shintel success: convuncing those to hold off on Ryzen because CFL " very likely to work with z270"
Also, making people (at least US) believe that you could get an 8700k for the same as a 7700k at launch. "Only a fool would think otherwise"

 

[schmide]

Your second post and you already start insulting people...

How sad. I never insulted you.

But since you went after my post count and you want an insult, by stating the above you're acting like a drama queen.

PS I may lurk, but I joined almost 10 years before you. I may or may not improve my post count, but you can't go back in time.

As many others, I prefer the issue wide to characterize the wide of a core. Why don't I use decode wide? First, because oversizing the front-end is a common technique. A decode wider than the optimal size is part of the arsenal of techniques used to reduce the time needed to achieve steady-state execution in a pipeline after this has been drained. Second, not all the input ISA are equivalent. Indeed 4-wide decode in ARM64 is not the same than 4-wide decode in x64, because one is RISC the other is CISC.

Again you gloss over the fact that Haswell+ and Zen have the same decode width which was the complaint in my initial post.

I don't prefer one or the other, nor do I care. Unless you want to make this a RISC CISC debate, then all gloves are off. (kidding)

Thus Zen is 6-wide and Haswell and above are 8-wide. And the ratio 8/6 is very close to the 20--30% IPC gap between both.

Yes there are cases where Haswell+ receives a 20%+ performance gap. There are also some cases where it's equal or may even lean in Zen's favor.

Zen is in some ways a 6+ because some instructions are fused into one pipe.

This is what should be discussed, not blanket statements generalizing a wide variety of units into a single number.

muxr was wrong. He wrote Zen could decode 6 instructions at once. He was wrong because Zen only can decode a maximum of four instructions.

and I explained that and gave a link to where the intent of his statement was correct. (which you ignored)

You're so into this pissing contest you can't even treat people with respect or use your knowledge to correct something that obviously had some validity.

Before launch, I predicted that Zen would shine in throughput workloads, whereas would fail in latency workloads. Time and reviews have given me the reason.

You seem to believe that latency and throughput have the same importance for a CPU, but it isn't true. Even AMD in its HSA specification acknowledge the existence of two classes of compute units: LCU and TCU.

LCU = Latency Compute Unit. CPUs are instances of LCUs.
TCU = Throughput Compute Unit. GPUs and other accelerators are instances of TCUs.

So the key parameter for a CPU is latency and Zen is lacking in this. AMD has tried to solve this deficiency, first developing a new AGESA version with a ~6ns latency reduction, and latter developing new AGESA versions, as the recent 1.0.0.6, with improved support for faster overclocked RAM. Overclocking RAM somewhat alleviates (hides) the latency problem in Zen.

AMD has designed a CPU that shines in throughput tasks that run better in other chips such as GPUs. Tasks such as rendering and encoding.

I did say Intel's ISA retires memory much better. I would; however, not characterize latency and throughput as of the same importance for any one general task. They are separate entities that affect how instructions pass through the system. You can pay a penalty for one, the other, or both.

I see the cache and memory system in less of an all encompassing manor. Latency is the cost of getting code into the cache. Once there how fast instructions can be processed is the throughput.

I would actually disagree that AMD is better at throughput. Intel is far better at moving data through the CPU their SIMD core is evidence of that.

To me it seems that AMD is slightly better at small loops and general instructions. Conditions, addressing, etc. How that would characterize into LCU or TCU is not for me to quantify.

I really don't care about predictions or who is right or wrong. PS I'm wrong a lot. Personally I think it's better to be wrong than tell half truths or overgeneralize something just to get your epeen going.

 

[Pieter3dnow]

Your second post and you already start insulting people...

As many others, I prefer the issue wide to characterize the wide of a core. Why don't I use decode wide? First, because oversizing the front-end is a common technique. A decode wider than the optimal size is part of the arsenal of techniques used to reduce the time needed to achieve steady-state execution in a pipeline after this has been drained. Second, not all the input ISA are equivalent. Indeed 4-wide decode in ARM64 is not the same than 4-wide decode in x64, because one is RISC the other is CISC.

Thus Zen is 6-wide and Haswell and above are 8-wide. And the ratio 8/6 is very close to the 20--30% IPC gap between both.

muxr was wrong. He wrote Zen could decode 6 instructions at once. He was wrong because Zen only can decode a maximum of four instructions.



Before launch, I predicted that Zen would shine in throughput workloads, whereas would fail in latency workloads. Time and reviews have given me the reason.

You seem to believe that latency and throughput have the same importance for a CPU, but it isn't true. Even AMD in its HSA specification acknowledge the existence of two classes of compute units: LCU and TCU.

LCU = Latency Compute Unit. CPUs are instances of LCUs.
TCU = Throughput Compute Unit. GPUs and other accelerators are instances of TCUs.

So the key parameter for a CPU is latency and Zen is lacking in this. AMD has tried to solve this deficiency, first developing a new AGESA version with a ~6ns latency reduction, and latter developing new AGESA versions, as the recent 1.0.0.6, with improved support for faster overclocked RAM. Overclocking RAM somewhat alleviates (hides) the latency problem in Zen.

AMD has designed a CPU that shines in throughput tasks that run better in other chips such as GPUs. Tasks such as rendering and encoding.

Juanrga if you can't win an argument like many others you start making up stuff. I have yet to find anything on topic from you in this discussion about the announcement of new Zen/Vega based apu instead you revert to your well known tactics not just on this message board but on many others you sidetrack.

https://hardforum.com/threads/amd-l...u-with-vega-graphics.1946744/#post-1043289784

This is the quality post #1 from you which is kind of weird because again you don't talk about anything but furthering your own agenda outside of the topic every time you steer clear from what is being discussed and get the conversation sidetracked into things actually no one cares about. To prove this you come up with stuff that is downright past what the topic is about you go one about details of Zen working from your point of view:

https://hardforum.com/threads/amd-l...u-with-vega-graphics.1946744/#post-1043289794

And actually no one cares but again you get the whole thread sidetracked you and your claim to be honest it is so far removed from this topic that it makes no sense whatsoever...

If you can get away with such nonsense in this forum because people are pretty laid back or lax. But that is no reason to do it each and every time ....
This is at the same time the problem why people stopped believing you at any point in time because of this, the forums option to ignore you is the most popular feature.

I just want to say is that I rather see you posting on topic then getting things off the topic , we were saying things about the new laptops with the apu featuring Zen and Vega and if that does not excite you then what are you doing here ?

 

[juanrga]

How sad. I never insulted you.

But since you went after my post count and you want an insult, by stating the above you're acting like a drama queen.

You insulted me and you continue doing it.

Again you gloss over the fact that Haswell+ and Zen have the same decode width which was the complaint in my initial post.

I just explained you why using the decode-size can be confusing to characterize the wide of a core. Check Table 3 here. The table here. The first paragraphs here. You can see how issue-wide is utilized to compare CPUs.

So stop using your ignorance of industry de facto standards to build fantasy conspiracy theories and then insulting people that has been using issue-wide since before Zen launch.

Yes there are cases where Haswell+ receives a 20%+ performance gap. There are also some cases where it's equal or may even lean in Zen's favor.

I was discussing average gap.

You're so into this pissing contest you can't even treat people with respect or use your knowledge to correct something that obviously had some validity.

Very interesting how much effort you employ on trying to hide/excuse his glaring mistake. He claimed I was "wrong". Me mentioning he was wrong and me giving the correct decode-wide for Zen makes me the bad guy. LOL

I did say Intel's ISA retires memory much better. I would; however, not characterize latency and throughput as of the same importance for any one general task. They are separate entities that affect how instructions pass through the system. You can pay a penalty for one, the other, or both.

I see the cache and memory system in less of an all encompassing manor. Latency is the cost of getting code into the cache. Once there how fast instructions can be processed is the throughput.

I would actually disagree that AMD is better at throughput. Intel is far better at moving data through the CPU their SIMD core is evidence of that.

And here you ignore the main point (even AMD agrees that latency is a more important metric for a CPU, and Zen has a latency problem), whereas ignoring that I was discussing throughput on (serial) code, not in SIMD code.

Let us stop here. You are wasting my time.

 

[juanrga]

Juanrga if you can't win an argument like many others you start making up stuff. I have yet to find anything on topic from you in this discussion about the announcement of new Zen/Vega based apu instead you revert to your well known tactics not just on this message board but on many others you sidetrack.

https://hardforum.com/threads/amd-l...u-with-vega-graphics.1946744/#post-1043289784

This is the quality post #1 from you which is kind of weird because again you don't talk about anything but furthering your own agenda outside of the topic every time you steer clear from what is being discussed and get the conversation sidetracked into things actually no one cares about. To prove this you come up with stuff that is downright past what the topic is about you go one about details of Zen working from your point of view:

https://hardforum.com/threads/amd-l...u-with-vega-graphics.1946744/#post-1043289794

And actually no one cares but again you get the whole thread sidetracked you and your claim to be honest it is so far removed from this topic that it makes no sense whatsoever...

If you can get away with such nonsense in this forum because people are pretty laid back or lax. But that is no reason to do it each and every time ....
This is at the same time the problem why people stopped believing you at any point in time because of this, the forums option to ignore you is the most popular feature.

I just want to say is that I rather see you posting on topic then getting things off the topic , we were saying things about the new laptops with the apu featuring Zen and Vega and if that does not excite you then what are you doing here ?

In first link I replied to OrangeKrush and said him we have to wait to reviews of RyZen mobile instead trusting (as he did) the performance reported in AMD slides. I complemented SighTurtle post about OEMs by mentioning how the Lenovo laptop has single-channel memory for the mobile RyZen, and I suggested to Pieter3dnow (you) to don't derail this thread on RyZen mobile with conspiracy theories.

In the second link I correct a post from Nightfire. He claims that RyZen mobile will be close to Intel mobile in ST because, Intel will be limited to "4.0 GHz ST" and "Ryzen seems to be able to match these clocks". In my reply I reminded him of the existence of KBL mobile chips that hit 4.2GHz in ST. So RyZen mobile will have a clock deficit. He also makes incorrect claims about SMT and HT regarding MT performance. And I corrected that as well.

So both links are on-topic and both are correcting/complementing posts were also on-topic.

If you don't want me saying that Lenovo RyZen laptop uses single-channel memory. If you don't want me to claim we have to wait to third-party reviews of Ryzen Mobile. If you don't want me to recall that RyZen mobile will have a clock deficit in ST, then just say it, but don't pretend that my posts are off-topic.

 

[JustReason]

You insulted me and you continue doing it.



I just explained you why using the decode-size can be confusing to characterize the wide of a core. Check Table 3 here. The table here. The first paragraphs here. You can see how issue-wide is utilized to compare CPUs.

So stop using your ignorance of industry de facto standards to build fantasy conspiracy theories and then insulting people that has been using issue-wide since before Zen launch.



I was discussing average gap.



Very interesting how much effort you employ on trying to hide/excuse his glaring mistake. He claimed I was "wrong". Me mentioning he was wrong and me giving the correct decode-wide for Zen makes me the bad guy. LOL



And here you ignore the main point (even AMD agrees that latency is a more important metric for a CPU, and Zen has a latency problem), whereas ignoring that I was discussing throughput on (serial) code, not in SIMD code.

Let us stop here. You are wasting my time.

Wrong. He never originally insulted you, unless you wish to infer correcting you as insulting you. You make FAR TOO MANY vague inferences to be taken as fact. Even your links have vague correlations to the point at hand. Even so far as you keep mentioning Latency as an AMD issue where AMD is ahead of Intel in all aspects except L3 where cross-CCX adds a bit. And again as I have asked no less than 5 times over these few months: where is the proof that the latency makes a HUGE impact in REAL WORLD usage? Stop being daft and answer directly the questions and give direct answers and points and there will be far less issues with your posts.

 

[pendragon1]

it wasn't an insult but he hurt your feeling by correcting you. tough!

 

[jardows]

So, how did this thread devolve from a discussion of Mobile Ryzen APU to who insulted who?

 

[gigaxtreme1]

So, how did this thread devolve from a discussion of Mobile Ryzen APU to who insulted who?

Back on track. Anyone have a real link to the webinar on Thursday?

 

[Nside]

Isn't too soon for the usual conspiracy argument?

While I would doubt intel directly paid for OEM preferential treatment, I do believe they gave OEMs deep discounts on intel processors, possibly with an understanding of how they wanted AMD processors to be handled.

I can only speculate from what I have witnessed. The first clue is that not a single OEM ran AMD's last APU lineup even close to their full capability. Underclocking and limiting the system to single channel memory was the norm. The numbers on desktop variants of weaker APUs from AMD were destroying the OEM AMD laptops in all-around performance, with no solid reason other than the OEMs purposely nerfed the laptop motherboards... At the same time, the prices were right up there with intel offerings that had dual channel, and utilized the full 25w TDP... This makes no business sense unless there was a deal in place between intel and OEMs...

The Clue that they were getting deep discounts on the processors was how low they could go on the pricing. I was actively watching desktop pricing last year, as I was tossing up whether to build a new system or just have my brother-in-law buy one I found on sale. I ended up pointing him to a Dell with an i7 7700 that was on sale for about $100 more than the processor by itself was selling for at the time. Now, that was a fairly regular occurrence last year, and possibly earlier, that I would see fairly high-end desktops selling that cheap from OEMs, so it wasn't a fire sale or anything. Unless they were getting processors super cheap, there is no way they could add all of the other components of that desktop, and still make any money. It had a 1TB HDD, Windows 10, 8GB or 16GB (can't remember) of DDR4 RAM, and roughly $75-100 (retail) GPU in it...

I honestly considered buying one for myself, Saving the CPU, salvaging/parting the rest just to save a little bit of money on future builds. I seriously hate selling proprietary or OEM junk on ebay though. Tried selling a Lenovo desktop motherboard 2 years back, thinking maybe someone out there had a fried system... I think I got 3 or 4 people asking if it will fit in their laptop or other manufacturers case before I decided to remove the listing.

 

[IdiotInCharge]

The first clue is that not a single OEM ran AMD's last APU lineup even close to their full capability.

...because they were trash.

And I'd certainly have preferred that they weren't, but they were. These Ryzen/Vega APUs look a lot more attractive.

 

[JustReason]

...because they were trash.

And I'd certainly have preferred that they weren't, but they were. These Ryzen/Vega APUs look a lot more attractive.

Really... trash? AMDs APUs stomped Intels iGPU and hence the single channel memory being such a huge negative. Carrizo actually was competitive against Intel in the mobile/laptop space and the superior chip when using iGPU solely.

Attention: Before any of you shills post some half assed graph of the expensive iris-pro, search for experiences with them and see that the graphs don't speak to actual game play.

 

[IdiotInCharge]

Really... trash?

High power usage, low battery life, anemic CPU?

You got it!

Basic conclusion? Don't use an old AMD APU if you don't have to. Extremely budget limited? Buy whatever you can. If you actually need to do work on a budget, consider not gaming.

But if you can, get a mobile Intel + discrete GPU setup, if you insist on mobile gaming.

 

[JustReason]

High power usage, low battery life, anemic CPU?

You got it!

Basic conclusion? Don't use an old AMD APU if you don't have to. Extremely budget limited? Buy whatever you can. If you actually need to do work on a budget, consider not gaming.

But if you can, get a mobile Intel + discrete GPU setup, if you insist on mobile gaming.

Now you are being disingenuous and ignorant. In most reviews the CPU portion was equal to or just under Intels comparable part. The iGPU just plain stomps Intel iGPU.

And to my first statement here: Do you imply that dual channel ram would make no difference at all? Come on! In the least that is intentional bias and trolling.

And lastly to infer anyone here is recommending the last series of APUs NOW is asinine. The point was whether the next gen Vega APUs would suffer the same poor implementation, by Intel doing all they know how to do: by whatever means, immoral or otherwise or manufacturers cutting corners again.

 

[walwalka]

I'm excited for these, the power draw looks to be better suited for mobile use. Hopefully they come to market with decent performance, as I'm in need of a laptop and this work be great.

 

[juanrga]

While I would doubt intel directly paid for OEM preferential treatment, I do believe they gave OEMs deep discounts on intel processors, possibly with an understanding of how they wanted AMD processors to be handled.

I can only speculate from what I have witnessed. The first clue is that not a single OEM ran AMD's last APU lineup even close to their full capability. Underclocking and limiting the system to single channel memory was the norm. The numbers on desktop variants of weaker APUs from AMD were destroying the OEM AMD laptops in all-around performance, with no solid reason other than the OEMs purposely nerfed the laptop motherboards... At the same time, the prices were right up there with intel offerings that had dual channel, and utilized the full 25w TDP... This makes no business sense unless there was a deal in place between intel and OEMs...

The Clue that they were getting deep discounts on the processors was how low they could go on the pricing. I was actively watching desktop pricing last year, as I was tossing up whether to build a new system or just have my brother-in-law buy one I found on sale. I ended up pointing him to a Dell with an i7 7700 that was on sale for about $100 more than the processor by itself was selling for at the time. Now, that was a fairly regular occurrence last year, and possibly earlier, that I would see fairly high-end desktops selling that cheap from OEMs, so it wasn't a fire sale or anything. Unless they were getting processors super cheap, there is no way they could add all of the other components of that desktop, and still make any money. It had a 1TB HDD, Windows 10, 8GB or 16GB (can't remember) of DDR4 RAM, and roughly $75-100 (retail) GPU in it...

I honestly considered buying one for myself, Saving the CPU, salvaging/parting the rest just to save a little bit of money on future builds. I seriously hate selling proprietary or OEM junk on ebay though. Tried selling a Lenovo desktop motherboard 2 years back, thinking maybe someone out there had a fried system... I think I got 3 or 4 people asking if it will fit in their laptop or other manufacturers case before I decided to remove the listing.

That is part of the problem. "Speculations" and "beliefs" cannot be used for accusations.

The problem that you mention about using single-channel in last APUs gen. was an engineering mistake from AMD. It had zero to do with imagined conspiracy theories involving Intel and OEMs.

AMD engineers joined both Carrizo lines in a common platform. But the physical/electrics requirements were different for APUs on each line. Motherboard engineers had three options: (a) to design and test two different motherboard lines, one for Carrizo another for Carrizo Little, ruining the common platform strategy introduced by AMD to reduce costs; (b) to design a common motherboard with Carrizo line needs as minimum common denominator, this would force engineers to route the signals of the memory slots in a way would be fully working when Carrizo APU was inserted in the socket, whereas half slots would stop working with Carrizo lite APU, evidently this would generate problems and confusion at the final user level; (c) to design a common motherboard with Carrizo little line needs as minimum common denominator, forcing engineers to route the memory slots in a way would be fully working when either Carrizo APU or Carrizo Little APU were inserted in the socket. Option (c) was chosen by motherboard engineers, it ensured both Carrizo and Carrizo Little APUs worked in the same mobo, as AMD required with the common platform approach, and it ensured all the slots to work. The counterpart for this option was that top Carrizo line worked in single-channel configuration. But motherboard engineers couldn't do miracles...

I have been actively watching forums during last years, and I always detect the same procedure: (i) overhype AMD products before launch, (ii) look for excuses when reviews shows a different picture, (iii) accuse Intel/Nvidia/OEMS/developers...

Mobile RyZen isn't out still and some people is already in stage iii, with accusations that Intel is paying OEM "to handicap Ryzen in the design department". LOL

My only remark, in that post from mine that you quote, was that people would wait to launch and reviews of Mobile RyZen before starting conspiracy theories again.

 

[JustReason]

That is part of the problem. "Speculations" and "beliefs" cannot be used for accusations.

The problem that you mention about using single-channel in last APUs gen. was an engineering mistake from AMD. It had zero to do with imagined conspiracy theories involving Intel and OEMs.

AMD engineers joined both Carrizo lines in a common platform. But the physical/electrics requirements were different for APUs on each line. Motherboard engineers had three options: (a) to design and test two different motherboard lines, one for Carrizo another for Carrizo Little, ruining the common platform strategy introduced by AMD to reduce costs; (b) to design a common motherboard with Carrizo line needs as minimum common denominator, this would force engineers to route the signals of the memory slots in a way would be fully working when Carrizo APU was inserted in the socket, whereas half slots would stop working with Carrizo lite APU, evidently this would generate problems and confusion at the final user level; (c) to design a common motherboard with Carrizo little line needs as minimum common denominator, forcing engineers to route the memory slots in a way would be fully working when either Carrizo APU or Carrizo Little APU were inserted in the socket. Option (c) was chosen by motherboard engineers, it ensured both Carrizo and Carrizo Little APUs worked in the same mobo, as AMD required with the common platform approach, and it ensured all the slots to work. The counterpart for this option was that top Carrizo line worked in single-channel configuration. But motherboard engineers couldn't do miracles...

I have been actively watching forums during last years, and I always detect the same procedure: (i) overhype AMD products before launch, (ii) look for excuses when reviews shows a different picture, (iii) accuse Intel/Nvidia/OEMS/developers...

Mobile RyZen isn't out still and some people is already in stage iii, with accusations that Intel is paying OEM "to handicap Ryzen in the design department". LOL

My only remark, in that post from mine that you quote, was that people would wait to launch and reviews of Mobile RyZen before starting conspiracy theories again.

Link required, because your word isn't.

 

[Pieter3dnow]

My only remark, in that post from mine that you quote, was that people would wait to launch and reviews of Mobile RyZen before starting conspiracy theories again.

Well there was one big hint it is not that bad this time around it seems that all the models have a decent screen and a resolution above 1366*768 which fucking drove me nuts when I saw another model with an apu in it. that screen resolution is so outdated yet many AMD featured laptops have this.

But benchmarks really the whole reason to buy a laptop is benchmarks ? I have yet to meet someone which I can take seriously on the computer front which told me "Hey I bought this laptop and it rocks in benchmarks" .

 

[bobzdar]

Totally stolen from hardware.info , sadly the introduction is only in Dutch ..

So no 2700u ddr4/2400 combo? That kind of sucks. I'm wondering what the price of these will be...

 

[Pieter3dnow]

So no 2700u ddr4/2400 combo? That kind of sucks. I'm wondering what the price of these will be...

This supposedly is the first wave of laptops the second one coming in 2018.

 

[noko]

Any with dual graphics? Vega 11? Too early for that at this point. Anyways AMD finally has a very strong APU.

 

[IdiotInCharge]

Any with dual graphics? Vega 11? Too early for that at this point. Anyways AMD finally has a very strong APU.

Honestly, dual-graphics only makes sense when both parts, integrated and discrete, are positively anemic.

Realistically if you're going to include a dedicated GPU, might as well dedicate the full CPU to CPU cores instead of spending die space and TDP on slow graphics.

[remember that graphics thrives on memory bandwidth, which means that the CPU will be starved of it, and that only works when both are relatively low-power as in APUs... dual graphics with a cheap discrete GPU is the only place that it makes sense, and that's a tiny niche...]

 

[noko]

Honestly, dual-graphics only makes sense when both parts, integrated and discrete, are positively anemic.

Realistically if you're going to include a dedicated GPU, might as well dedicate the full CPU to CPU cores instead of spending die space and TDP on slow graphics.

[remember that graphics thrives on memory bandwidth, which means that the CPU will be starved of it, and that only works when both are relatively low-power as in APUs... dual graphics with a cheap discrete GPU is the only place that it makes sense, and that's a tiny niche...]

Plus dual graphics use to suck in the past - another hurdle. I don't know if Polaris and Vega would play nice together. There was a few games where dual graphics worked OK in.

 

[IdiotInCharge]

Plus dual graphics use to suck in the past - another hurdle. I don't know if Polaris and Vega would play nice together. There was a few games where dual graphics worked OK in.

Sure; but like I said, it's a tiny niche. It'd certainly be nice if that weren't the case, and AMD could possibly do an 'Iris Pro' thing and put some external cache on-package to help with very limited bandwidth of CPU memory, but that just increases the bill of materials more toward the price of including a far superior discrete GPU over an anemic discrete GPU or none at all.

Really, if they can get some good memory speeds on the APUs, they should be decent, and since Ryzen is more than 'close enough' for most users' use cases, AMD might find a decent market.


[on balance, I can play stuff like League of Legends on my i7-7500U ultrabook, which is Intel dual-core, at a solid 60FPS at 1080p if I bury the settings- so the mobile Intel graphics might very well be 'enough' for many, and we can reasonably expect Intel's mobile CPUs to remain both faster and have better battery life next to AMD's first mobile Ryzen/Vega APU release]

 

[Bankie]

Really, if they can get some good memory speeds on the APUs, they should be decent, and since Ryzen is more than 'close enough' for most users' use cases, AMD might find a decent market.


[on balance, I can play stuff like League of Legends on my i7-7500U ultrabook, which is Intel dual-core, at a solid 60FPS at 1080p if I bury the settings- so the mobile Intel graphics might very well be 'enough' for many, and we can reasonably expect Intel's mobile CPUs to remain both faster and have better battery life next to AMD's first mobile Ryzen/Vega APU release]

The thing that caught my eye was that AMD's benchmarks show LoL running at 59fps at 1080p MEDIUM settings. That's still pretty weak even if it is substantially faster than Intel's IGP.