AMD interested in reviving the math Co-Processor

interesting. still remember getting my first pentium 1 66mhz and it had a broken math co-processor, was the very first batch haha
 
That's hot. I hope they do it. Any extra co-processors on my board is a plus, regardless of their use... makes my sig longer :rolleyes:
 
interesting.. those of you who know a bit more about the actual cpu architecture than i, what types of data and calculations does the co-proc normally handle? :D
 
though so. so why on earth is AMD also working on K8L, which doubles the number of FPU units? ;)
though it seems this is kinda similar to what intel is doing these days.. a step backward to go forward.
 
I wouldn't expect this to impact the desktop market. Unless AMD plans on putting a second HTT bus on their desktop CPUs, you can't connect directly to the CPU. If you have to go through the chipset anyway, you might as well just buy the PCIe card, it will do the same thing.

You really have to get to the 8xx Opterons to see major benifit from this (though certianly a 2xx chip in one socket and a co-processor type module in the other has promise to specilization). Connected up through something like the Horus chipset where only one HTT link is required for CPU <-> CPU communications, and you tack on an ecryption/decryption unit to another HTT link and a vector processor on the last HTT link you've some impressive scalability along with tons of dedicated hardware for your job.
 
(cf)Eclipse said:
hmmm, perhaps we found a new use for some of those 1207 pins in socket F? :D

1206 ground pins and one power pin ;)

ya math co-proc is FPU/ALU boost for sure, we'll see what happens.
 
$BangforThe$ said:
All of which will drive up power consumption . Not a good idea.
meh, i'd be surprised if it's more than 10-15 watts.. if the performance inprovement is anywhere near what it should be, it's easy to compensate by reducing clocks some.. ;)
 
$BangforThe$ said:
All of which will drive up power consumption . Not a good idea.

Their chips already max at about 20W below their TDP, they can spare some power.
Besides, how much power does that math co-processor take?
 
In the days of old, the 486sx was without math coprocessor, which if memory serves, the math-co was nothing more than a 486 with FPU enabled. The SX was the 486 with FPU disabled.

Correct me if I'm wrong here guys, but thats what I got from it.
 
Before that, a math coprocessor was a totally seperate chip that went on the motherboard.
 
$BangforThe$ said:
All of which will drive up power consumption . Not a good idea.

According to Clearspeed their flagship processor disipates a "maximum of 10 watts"

Thats like saying 512k of cache is better because 1meg is double the transistors which will increase power consumption.
 
yea, didn't really get into that here, or much in the way of study either. The 386 and the 486SX were virtually the same chip, no?
 
pOwErEd By NOS said:
According to Clearspeed their flagship processor disipates a "maximum of 10 watts"

Thats like saying 512k of cache is better because 1meg is double the transistors which will increase power consumption.

Hah, AMD gets back that power consumption back by switching to DDR2 anyway. AMD will still be a highly power efficent desktop platform (even with that awful outdated 90nm!)
 
heheh.. the return of the DX chip... (vs SX... where they actually zapped the link to the math co with a laser to make a less powerful chip).. but I guess that was the Insmell, er, Intel naming scheme..
 
This makes one wonder why there was a move aware from math co-proc's in the first place, doesn't it?

I am sure that there are some limitations to the clearspeed design. I sincerely dobut that it has branch prediction etc. Nonetheless, if this really happens, it is a move towards something that I had been expecting for a while: The CPU will move away from actually doing computations to scheduling/ directing the system interaction. Like a GPU, there will soon be more ASICs to take care of certain calculations much more efficiently than a CPU can. This math-processor, network processor.
In the extreme the CPU would fetch + decode instructions and feed them to the required ASIC for exectuion, reassembling what is needed once it gets the return values.
 
I dont know alot abbout processor design and what not so I present this question...

Why dont they just integrated this "Math Co Processor" Onto the Die andd make a new architecture? Why have a "seperate" chip or whatever you know?

Its like... we have integrated FPUs and ALUs etc.. they are not sitting "off by them selfs" why cant we just do that with this too?
 
USMC2Hard4U said:
I dont know alot abbout processor design and what not so I present this question...

Why dont they just integrated this "Math Co Processor" Onto the Die andd make a new architecture? Why have a "seperate" chip or whatever you know?

Its like... we have integrated FPUs and ALUs etc.. they are not sitting "off by them selfs" why cant we just do that with this too?

Co processors are generally very specialized devices that a very powerful in a specific task. But most people don't have a great need for that specific task. Back in the math coprocessor days of the 386/486 chips, very few people used FP intensive software. What little FP math they did do could be emulated through software (much slower and less efficient than a hardware FPU, but sufficient for most people). The added cost of a math co processor was something most home users couldn't justify at the time.

As FP math became a desired feature for the average user (read: we wanted to play 3d and pseudo-3d games), the FP co processor became a standard feature, and migrated into the CPU as a standard component.

Right now, there are many niche markets for specalized hardware. Scientific computing would be well served by tacking on a vector coprocessor capable of handeling several 128bit vectors per clock. Large secure databases / webservers would see great benifit from dedicated encryption / decryption hardware ( Sun's Niagara chip includes an encryption / decryption unit for each of its 8 cores, but only one FPU per die). Very specific mathmatical functions would be useful for fluid dynamics and other physics simulations.
None of that is particularly useful to the average user. So nobody is going to be spending the die space and transistors and time to integrate those into the CPU. Like with the FPU, if some functionality of an add on becomes both ubiquitous in use, and economical in implementation we may seen new functionality added to the die. In fact that has already happened to an extent with Intel. While SSE vectors were never handled by a co-processor so to speak, they were emulated on the FPU in P3. In P4 and Conroe, they use an SSE vector unit to emulate x87 FP math. Now that was realy intel driving the software market towards the new hardware (and finally gaining some traction in how x86-64 handles FP math), but the idea is the same: specialized hardware has become the standard for everyone so it's part of the CPU proper.
 
Back
Top