AMD drops Threadripper3 from latest roadmap-Tom's

Zarathustra[H] said:
Again, if Ryzen has 16 cores and 40 PCIe lanes off of the chipset, what benefit does Threadripper still provide? How much money is quad channel RAM worth to you?

By the sounds of it, Ryzen IS the new AMD HEDT platform.

On a side note, can anyone tell me what the T in HEDT stands for?
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If I build what I want I will need 56 PCI-e lanes. I think you are also missing that some of those 40 lanes are shared. I'm rather annoyed with my 2700X that I have to choose between the second NVME slot and the 3rd 8x/16x slot. (yes I know it has less lanes to start with)

Most of the work I'm doing happens on the GPUs so Storage I/O and Memory bandwidth mean more to me than cores but they do come in handy for the pieces I can't hand off to the GPU

Build would be

2x GPU for 32 Lanes
4x NVMe for 16 Lanes
1x 10Gbe for 8 Lanes

For a total of 56 even if I drop one of the GPUs I'm at 40 lanes and will likely have some weird performance issues with some of the lanes shared with the CPU uplink and other onboard peripherals

Box is for content creation (Editing, Transcoding, 3D animation) and I've been dabbling in AI/ML for autonomous drones so the Memory bandwidth will come in handy as well.
 
DeChache said:
If I build what I want I will need 56 PCI-e lanes. I think you are also missing that some of those 40 lanes are shared. I'm rather annoyed with my 2700X that I have to choose between the second NVME slot and the 3rd 8x/16x slot. (yes I know it has less lanes to start with)

Most of the work I'm doing happens on the GPUs so Storage I/O and Memory bandwidth mean more to me than cores but they do come in handy for the pieces I can't hand off to the GPU

Build would be

2x GPU for 32 Lanes
4x NVMe for 16 Lanes
1x 10Gbe for 8 Lanes

For a total of 56 even if I drop one of the GPUs I'm at 40 lanes and will likely have some weird performance issues with some of the lanes shared with the CPU uplink and other onboard peripherals

Box is for content creation (Editing, Transcoding, 3D animation) and I've been dabbling in AI/ML for autonomous drones so the Memory bandwidth will come in handy as well.
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Fair. That represents a pretty small slice of even the HEDT market though, I'd imagine.

Most of us are looking to put a single GPU in there and then have slots left over for NVMe or other peripherals.

The fact that the CPU uplink from the chipset is Gen4 now, means the bandwidth sharing is less of a big deal, as most expansion cards will be Gen1 thorough Gen3. Especially if they - as I suspect - up the uplink to 8x.

Your second GPU does throw things for a loop though. Whether or not there will be a practical difference remains to be seen though. GPU's really don't use all the bandwidth of the 16 lanes they have very often, if ever.

Thing is, the more reasonably priced x299 CPU's are similarly limited. The 7640x and 7740x only have 16 lanes. The 7800x and 7820x only have 28.

You have to go up to the $1,000 7900x to get 44 lanes, and if that's not enough you need to opt for a Xeon W and then you only get 48, not the 64 Threadripper provides. It also means lower clocks, if that is a concern to you.

At that point it's Xeon vs Epyc, unless a new variant of Threadripper rears its head.
 
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Zarathustra[H] said:
Fair. That represents a pretty small slice of even the HEDT market though, I'd imagine.

Most of us are looking to put a single GPU in there and then have slots left over for NVMe or other peripherals.

The fact that the CPU uplink from the chipset is Gen4 now, means the bandwidth sharing is less of a big deal, as most expansion cards will be Gen1 thorough Gen3. Especially if they - as I suspect - up the uplink to 8x.

Your second GPU does throw things for a loop though. Whether or not there Will be a practical difference remains to be seen though. GPU's really don't use all the bandwidth of the 16 lanes they have very often, if ever.

Thing is, the more reasonably priced x299 CPU's are similarly limited. The 7640x and 7740x only have 16 lanes. The 7800x and 7820x only have 28.

You have to go up to the $1,000 7900x to get 44 lanes, and if that's not enough you need to opt for a Xeon W and then you only get 48, not the 64 Threadripper provides. It also means lower clocks, if that is a concern to you.

At that point it's Xeon vs Epyc, unless a new variant of Threadripper rears its head.
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I know I'm not the common use case but there market for machines like I mentioned exist.

I will correct one thing above. 3D graphics don't use the full 16X slot but compute use does. Especially if you are moving a lot of data in and out of VRAM. Its a totally different world than gaming.

Right now most with the needs I listed are already running Xeons in either single or dual (dual usually means they need the PCI-e lanes)

Or they are going to HPC groups and asking for cycles
 
DeChache said:
I know I'm not the common use case but there market for machines like I mentioned exist.

I will correct one thing above. 3D graphics don't use the full 16X slot but compute use does. Especially if you are moving a lot of data in and out of VRAM. Its a totally different world than gaming.

Right now most with the needs I listed are already running Xeons in either single or dual (dual usually means they need the PCI-e lanes)

Or they are going to HPC groups and asking for cycles
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Sounds like you need a EPYC based tower Server chassis/mobo. Only problem is the lack of PCIE X 16 slots. But you would have your PCIE lanes that is for sure.
 
I have been pretty impressed by my current motherboard and CPU combination.
 
If it's out of the 2019 roadmap, it will be at the beginning of 2020. There is no doubt about that. They announced it, and professionals are counting on it.
However I am more ready to think that this roadmap has limited slots to fill until an unknown date. Could be october. And Threadripper doesn't fill in. It comes after.
 
This is really quite frustrating. Zen and Zen+ had decent model announcement to launch timeframes, with Ryzen coming out in early spring and with Threadripper to follow in the summer. When this year's Zen2 Ryzen was delayed several months, I was worried especially about Threadripper but hoped that it would arrive by September or October at the latest. If it is off the lineup completely and pushed until early 2020 that's a big issue, as it means that it will launch around when Zen2+ is announced, which is poor timing. AMD did well by launching their HEDP reasonably soon after mainstream, but I'd hate for them to get on Intel's schedule of the latest HEDP being based on CPU tech one generation back.

Some discussed if they'll rebrand Threadripper, merge it into Epyc etc... but whatever they do I hope they just don't delay Zen2 Threadripper too long. They're all ready behind schedule this year and that delay can be understood as it stands at least for Ryzen, but if they push HEDP until much later that will be very frustrating indeed, especially as someone who was looking forward to a Threadripper Zen2 system this summer/early fall
 
RanceJustice said:
This is really quite frustrating. Zen and Zen+ had decent model announcement to launch timeframes, with Ryzen coming out in early spring and with Threadripper to follow in the summer. When this year's Zen2 Ryzen was delayed several months, I was worried especially about Threadripper but hoped that it would arrive by September or October at the latest. If it is off the lineup completely and pushed until early 2020 that's a big issue, as it means that it will launch around when Zen2+ is announced, which is poor timing. AMD did well by launching their HEDP reasonably soon after mainstream, but I'd hate for them to get on Intel's schedule of the latest HEDP being based on CPU tech one generation back.

Some discussed if they'll rebrand Threadripper, merge it into Epyc etc... but whatever they do I hope they just don't delay Zen2 Threadripper too long. They're all ready behind schedule this year and that delay can be understood as it stands at least for Ryzen, but if they push HEDP until much later that will be very frustrating indeed, especially as someone who was looking forward to a Threadripper Zen2 system this summer/early fall
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What are you talking about?

3rd gen Ryzen wasn’t “delayed several months”

Where did you get that from?
 
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_mockingbird said:
What are you talking about?

3rd gen Ryzen wasn’t “delayed several months”

Where did you get that from?
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In comparison to the release dates of the Zen and Zen+ versions (ie March/April for Ryzen, August for Threadripper), both forms of the 3rd gen are scheduled to release later than the scheme for the previous two revisions
 
RanceJustice said:
In comparison to the release dates of the Zen and Zen+ versions (ie March/April for Ryzen, August for Threadripper), both forms of the 3rd gen are scheduled to release later than the scheme for the previous two revisions
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Every generation is different and with different deliverables schedules and difficulties. It is silly to assume that a company will launch their products in the same month, or after similar time intervals every time. That's just not the way things work in the real world.

1700x launched in February 2017. 2700x launched in April 2018, this doesn't say anything about when the 3xxx series will launch. (Even though it is coming in June, and by random coincidence that makes it 14 months between each launch...)

Companies set targets for projects based on desired market launch dates, technical complexity, the amount of work that remains, the resources they have on hand, and the lengths of the projects will be different every time. There is no such thing as a fixed length development and release schedule.

There is absolutely nothing to suggest that 7nm Ryzen is being launched at any other time than when AMD planned to launch it at the beginning of the project.

So no, it is not delayed.
 
DeChache said:
If I build what I want I will need 56 PCI-e lanes. I think you are also missing that some of those 40 lanes are shared. I'm rather annoyed with my 2700X that I have to choose between the second NVME slot and the 3rd 8x/16x slot. (yes I know it has less lanes to start with)

Most of the work I'm doing happens on the GPUs so Storage I/O and Memory bandwidth mean more to me than cores but they do come in handy for the pieces I can't hand off to the GPU

Build would be

2x GPU for 32 Lanes
4x NVMe for 16 Lanes
1x 10Gbe for 8 Lanes

For a total of 56 even if I drop one of the GPUs I'm at 40 lanes and will likely have some weird performance issues with some of the lanes shared with the CPU uplink and other onboard peripherals

Box is for content creation (Editing, Transcoding, 3D animation) and I've been dabbling in AI/ML for autonomous drones so the Memory bandwidth will come in handy as well.
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This kinda gets at where the lanes go. I'm solidly in the single GPU camp, but otherwise ... Nvme(s), NICs, SAS/RAID whatever, or those flash HBA's. It adds up.

Edit: I will strangely miss the Threadripper moniker.
 
Another issue for Ryzen chips not meeting needs in the HEDT would is three 64GB memory limit.
 
bbenz33 said:
Another issue for Ryzen chips not meeting needs in the HEDT would is three 64GB memory limit.
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I thought TR supported up to 2 TB of quad channel DDR4, no?

It has been a while - the TR boards I looked at had 8 dimm sockets. Set up as 2 banks with their own memory controller and, if I remember right, a ring type bus in the CPU package moving data around to dies not connected to ram.

-Edit-

Ah you mean Ryzen Gen 2 taking the place of TR.

I read about some new 32gb dimms that should work with Ryzen on existing boards taking the max up to 128 gb, expensive though.

Whats to stop some new AM 4 boards from having 6, 8, 12, or 16 dimm sockets?
 
Whats to stop some new AM 4 boards from having 6, 8, 12, or 16 dimm sockets?
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2 channel DDR4 limit. There is are specific limits to the number of slots per channel and even the speed if the dimms are double sided.
 
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Elf_Boy said:
I thought TR supported up to 2 TB of quad channel DDR4, no?

It has been a while - the TR boards I looked at had 8 dimm sockets. Set up as 2 banks with their own memory controller and, if I remember right, a ring type bus in the CPU package moving data around to dies not connected to ram.

-Edit-

Ah you mean Ryzen Gen 2 taking the place of TR.

I read about some new 32gb dimms that should work with Ryzen on existing boards taking the max up to 128 gb, expensive though.

Whats to stop some new AM 4 boards from having 6, 8, 12, or 16 dimm sockets?
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Quite a lot actually. The memory controller has to be designed to accept that much memory. Currently, its limited to 64GB on 1xxx and 2xxx series Ryzen CPUs. There are chipset and I/O considerations as well. Addresses for option ROMs have to be mapped to memory. Direct memory access for hardware, etc. all come into play. Beyond that, the CPU's memory controllers have to be configured to accept additional memory channels.

drescherjm said:
2 channel DDR4 limit. There is are specific limits to the number of slots per channel and even the speed if the dimms are double sided.
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Exactly. Back in the Pentium III days, there was at least one board I vaguely remember which had six DIMM slots or something like that. To use all six required using single sided DIMMs in the last two slots. Why this was done that way is beyond me. But this is an example of such constraints. You could theoretically increase the number of DIMM slots by making them all single ranked, but that would limit you to using single ranked modules. There are other concerns here as well such as trace path design and keeping all of those slots close enough to the CPU's IMC to avoid signaling problems inherent to that design.

There is more to Threadripper than PCIe lane count and how much memory it can support. We could also see something in the future in the form of a Threadripper CPU, which is a higher clocked Epyc without dual socket support. This could mean AMD is moving to an Intel crushing 128PCIe lanes and eight memory channels in the HEDT segment. One of the problems with the 2990WX is that its limited memory bandwidth hurts it compared to its Epyc counterpart in some applications. Or it could mean that we won't be seeing any more Threadripper because it doesn't sell enough to justify its existence. AMD can functionally achieve most if not all of what Threadripper does in the mainstream segment in Ryzen 2. We'll have to wait and see.
 
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From Tom's apparently Tum will release a screenshot later
"TUM_APISAK left an endnote that he might share a screenshot of the processor soon. We'll update the article once the screenshot is available."
 
It seems like this is simply a capacity decision.

TSMC may just not be able to provide enough 7nm dies yet to support Ryzen, Epyc, Vega and Threadripper all at once, especially since other customers (Apple) may be demanding some of that same capacity.

Rumors seem to suggest Threadripper is not going away, just delayed to 2020 as a result. Not sure if this means TSMC gas more capacity coming online, if other customers have less load then, or if they are counting on yield improvements.

If I had the choice I'd go with Threadripper and it's 64 PCIe lanes. PCIe lanes are very important to me.

That said, per core performance is also very important to me, so I am unwilling to buy previous gen cores on an older process

The one thing they are delivering in spades in both platforms is the one things I care least about, and that is core count.

It kind of sucks that you have to choose between per core performance and PCIe lane count.

With the rumored 40 lanes coming off the chipset for x570 however, I may be able to live with a Ryzen chip. It remains to be determined and is highly implementation dependent.

If they have provided sufficient uplink bandwidth that the 40 chipset lanes aren't too bandwidth starved and the multiplexer in the x570 chipset doesn't have other issues (like latency) I may just be able to live with it.

I won't be fully happy about it, as I really want my "no compromises" platform, but it may be enough that I just deal with it.

This is what I am going to be looking for in reviews on launch. The PCIe lanes question is undoubtedly the make or break variable regarding whether or not I can make myself buy a 7nm Ryzen, so I'll be watching closely.
 
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TR3 will likely just be delayed a few months. I'd expect 20, 24 and 32 core models. Top end Ryzen gets 16 so not much of a need to offer that on TR3.

I want to upgrade to Zen 2 but using a 1070 at 3440x1440/60hz I wouldn't see any real improvement over my 4c/4t.
 
DeChache said:
If I build what I want I will need 56 PCI-e lanes. I think you are also missing that some of those 40 lanes are shared. I'm rather annoyed with my 2700X that I have to choose between the second NVME slot and the 3rd 8x/16x slot. (yes I know it has less lanes to start with)

Most of the work I'm doing happens on the GPUs so Storage I/O and Memory bandwidth mean more to me than cores but they do come in handy for the pieces I can't hand off to the GPU

Build would be

2x GPU for 32 Lanes
4x NVMe for 16 Lanes
1x 10Gbe for 8 Lanes

For a total of 56 even if I drop one of the GPUs I'm at 40 lanes and will likely have some weird performance issues with some of the lanes shared with the CPU uplink and other onboard peripherals

Box is for content creation (Editing, Transcoding, 3D animation) and I've been dabbling in AI/ML for autonomous drones so the Memory bandwidth will come in handy as well.
Click to expand...

If it winds up working the way I think/hope it will, you'll get close, but not quite there.

28x Gen4 lanes off of the CPU.
- 8x Gen4 for uplink to chipset
- 16x Gen4 of these will be available for the primary GPU slot.
- 4x for other use

40x lanes (- uplink lanes) off of the chipset
- 32x available.

So you get 16x + 4x directly from the CPU + 32x from the chipset.

So we are talking a total of 52x lanes.

Now, the 32x off the chipset then share the bandwidth of the uplink lanes. If it winds up being 8x Gen4, that's the equivalent of 16x Gen3 bandwidth.

So depending on what gen devices you plug in, and how many of them hit 100% utilization at the same time, this can either be a problem, or it can wind up a complete non issue.

In my application I have:
- GPU (16x Gen3)
- Dual 10gig NIC (8x Gen2)
- Sound Card (1x Gen 1)
- NVMe1 (4x Gen 3)
- NVMe2 (4x Gen 3)

So, I'd imagine the GPU and one of the NVMe drives go straight to the CPU.

That leaves:
- Sound Card (1x Gen1)
- NIC (16x gen1 equivalent)
- NVMe (16x gen1 equivalent)

So, 33 gen1 equivalent utilizing the bandwidth of the 8x Gen4 uplink lanes (64x Gen1 equivalent)

So even if all devices hit 100% load at the same time, I'm only utilizing 33/64 ~52% of the total bandwidth.

So, as long as there aren't any bad latency implications of the multiplexer in the chipset or anything else, this would actually work for me. I could probably add another two NVMe drives without overwhelming the uplink bandwidth.
 
Ideally you want the devices that talk to each other on the same segment. There is a (relatively) large latency hit when you have to traverse the bridge. I would actually put networking and peripherals next to the CPU and everything else on the chipset... For my use case but outside of server boards I haven't seen the ability to know or adjust what drives which lanes.

So yeah the NVMe drives going through the bridge probably not a big deal but if the GPUs are to work together they need to be on the same segment. You wouldn't want one talking directly to the CPU and one on the chipset. At least in my use case.

Again for 98% of users this will be fine. But its not close to ideal for the workstation market.
 
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