Fundamentally the 3d stacking tech was developed with mobile phone SoC in mind where these temperatures and voltages would never be a thing so that has to be remembered first.This is what bothered me. Ever since i read about (and probably more than once from you discussing it in previous threads) this limitation with the 5800X3D, the idea was that they didn't launch the 7000 series 3D until they have a fix that wouldn't require the compromises of the previous generation. I'd hoped that they would have been able to find a compound stable enough to make it equivalent to the standard 7000 series in terms of wattage, allow the same OC and frequency, and was hoping for full both CCX unit vcache. I guess the question here is A) how much of a compromise is this , really and B) is this something that could have been solved in another few months of development and/or an admission that this is the best we get for this generation try again in the fall? Will there be a chance that in a few months there will be some sort of 7990X3D that is a 170w 4.5>5.7ghz standard boost, overclockable, 2 CCX 3D VCache on both sides chip?
Of course its likely that even as it is the 7950X3D is going to be an absolute monster as it is, but I have to wonder what problems this will create and if it isn't something that could have been resolved with a bit more time? What will be the overclock potential and how hard will things be locked down? What will be the frequencies of the 3D CCX vs the standard? Will users have the ability to pick which one they want applications to run upon and by default how good will it estimate what to do? Will users be able to easily override any 'default' decisions without having to use proprietary manual thread-pinning applications? Thinking of overclocking , Asus anyway was noteworthy for bringing the "dynamic OC" feature implemented on the 5000s-era Dark Hero into all their X670E boards (or definitely all their ROG or named boards at least) that allows users to both get the best of PBO2 style auto-to-threshold single/few core performance and when needed swap over to many/all core manually set turbo OCs. I wonder how this will be affected by a chip with both CCXs populated but heterogeneous vcache and potentially different max frequencies? Given the quote above that Riev90 cites, the "bare chiplet can access stacked cache in the adjacent chiplet but this isn't optional and will be rare", more info on that situation will be interesting.
Ultimately we'll get more info in the lead up to and after launch, but it will be nice to see it behaves in edge cases and if this design decision was a best-of-all-worlds or a necessitated compromise.
The main reason for the delay was less about the voltage restrictions and more about the physical act of lining up the silicon, the mechanical process that does this was problematic and failed too often for commercial viability and that is why it was delayed.
Ultimately there isn't really a means by which they can use the stacked cache at full voltages and not run into a problem with it melting down, as the melting point of the adhesive must be lower than the maximum temperature of the silicon otherwise just applying it would damage the silicon. They then have to further limit the operation of the CPU so that it can't run itself into a situation where under circumstances it could get hot enough to re-melt that adhesion layer.
I doubt we would see much overclocking potential for the x3D parts, and I trust AMD to have gotten the timings and frequencies to a point where there wouldn't be many benefits in doing so, ram speeds as always are likely going to be the better option.
Seeing this design what I want to know is when the non-stacked CCX accesses the cache on the stacked side is it still faster than if the extra cache wasn't there at all?
If it is still faster, what are the possibilities that down the road AMD makes use of their Infinity Fabric more and like their MCDs on the RDNA 3 stuff and have the extra cache external to the CCX, it may not be as fast but if it is faster overall and less complicated and lets them use a cheaper process then overall it would be better to a degree no? This would be similar in concept to what Intel has decided to do with the new Xeons and offer Ram on the dye to speed up operations.
Either way, the chips are cool even if they are a stepping stone and I really look forward to reviews. the very fact that Intel and AMD are having to innovate and go to such lengths to one-up each other is proof that there is strong competition there and it's resulting in some advancements that the geek side of me is going crazy for.