2nd Gen HBM2 Aquabolt Starts Mass Production

FrgMstr

Just Plain Mean
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While I am a bit unsure of the "Aquabolt" name, there is no doubt that HBM is finding its place in the industry, and now HBM2 is in production by Samsung. HBM2 will deliver 2.4Gbps per pin at 1.2v, compared to the original HBM's transfer rate of 1.6Gbps at 1.2v. The improvement equates to a overall transfer rate of 307GBps. Other improvements include and increased number of thermal bumps which should provide better cooling and an additional protective layer at the bottom which will give the package better overall physical strength to protect it from damage.

With these improvements, a single Samsung 8GB HBM2 package will offer a 307 gigabytes-per-second (GBps) data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth.* Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth., which will improve overall system performance by as much as 50 percent, compared to a system that uses a 1.6Gbps HBM2.
 
Is it even possible to saturate a memory bus with that much bandwidth?
 
I know this is mostly aimed at graphics cards, but I do hope samsung has some plans to bring this to system ram.
 
I know this is mostly aimed at graphics cards, but I do hope samsung has some plans to bring this to system ram.

Was coming here to say/wonder the same thing. Might need a different form factor than DDRx DIMMS? One of the things I remember from the original HBM announcements was that it was going to use a ridiculously-wide data bus: hundreds of address lines, not a 64-bit bus as is typical.
 
Man, I really hope Nvidia comes out with this in the next-gen high end card, 1080ti was a nice boost and it got me to upgrade most my other components, but now it doesn't really allow me to max out.. I'm ready to upgrade to the next level (titans are just not worth it for very little gain).

I too keep waiting for better RAM options, DDR4 is what 8 years old and has actually regressed in performance across that time? we use to have 2100 speeds but CL9's, now we see 4000 but CL 27 while the price rises... I'm on my 20th year waiting for the BIOS to die, and 30th year for the motherboard to change. long live ancient-ATX - following those trends we'll see DDR4 around for next 60+ years in same form factor.
 
AMD should've went for a small royalty fee for every HBM/HBM2 chip made.

AMD doesn't supply any of the know-how needed to develop a ram standard. They just supply the purchase order (guaranteed design win for Fiji) and the desired requirements. And of course the test time to debug the new HBM controller and the interface with the new chips.

A small tech company like AMD has the barest knowledge of how to make a memory chip fast, as cheap as it can be and low-power. They can barely compete in two major markets at once.
 
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AMD doesn't supply any of the know-how needed to develop a ram standard. They just supply the purchase order (guaranteed design win for Fiji) and the desired requirements. And of course the test time to debug the new HBM controller and the interface with the new chips.

A small tech company like AMD has the barest knowledge of how to make a memory chip fast, as cheap as it can be and low-power. They can barely compete in two major markets at once.

You're confused.

Did AMD not co-develop HBM with Hynix?

https://www.kitguru.net/components/...ng-usage-of-hbm-and-do-not-collect-royalties/
 
AMD invented HBM, well at least that is what they claimed and worked with Jedec to standardize it.

https://www.amd.com/en/technologies/hbm said:
A legacy of enabling industry-wide innovation
AMD has a long history of pioneering innovations, spawning industry standards and spurring the entire industry to push the boundaries of what is possible. HBM is just the most recent in an impressive list that spans CPUs, graphics, servers, and more:

  • X86-64: The 64-bit version of the x86 instruction set found in all modern x86 CPUs
  • Wake-On-LAN: Co-invented w/ HP, this revolutionary computer networking standard enables remote computer wake-up
  • GDDR and now HBM: Pervasive industry standards for high-performance memory, invented by AMD with contributions from the Joint Electron Device Engineering Council (JEDEC) and industry partners
  • The first multi-core x86 processor: AMD’s Opteron™ 100 Series CPU was famously the first to bring multi-core computing to the PC space
  • DisplayPort™ Adaptive-Sync: Implemented by AMD as FreeSync™ technology, this VESA-ratified AMD proposal eliminates stutter for smoother gameplay
  • First on-die memory controller for x86: AMD’s “Hammer” architecture was first to integrate a memory controller onto consumer CPUs for peak performance
  • Mantle: The first low-overhead PC graphics API, sparking a revolution that now spans the entire PC graphics industry
  • First on-die GPU: AMD’s Accelerated Processing Units (APUs) were the first to explore the integration of a GPU with the CPU, eliminating the need for a bulky external GPU for compact or inexpensive PCs
With HBM, AMD is set to once again revolutionize the industry, from next-level gaming to VR and beyond.
 
AMD invented HBM, well at least that is what they claimed and worked with Jedec to standardize it.

Hynix doesnt even mention AMD in their papers. Being willing to be the first customer and co developing is quite different. AMD havent made a memory controller either for ages because they are unable. They license 3rd party designs.

It´s about equal to claim that Nvidia developed GDDR5X and GDDR6.
 
Hynix doesnt even mention AMD in their papers. Being willing to be the first customer and co developing is quite different. AMD havent made a memory controller either for ages because they are unable. They license 3rd party designs.

It´s about equal to claim that Nvidia developed GDDR5X and GDDR6.
AMD started the ball rolling, has patents, worked with Hynix and Jedec. Who cares what Hynix mentions now, it is Jedec standard which others can use to promote industrial growth overall.
https://en.wikipedia.org/wiki/High_Bandwidth_Memory said:

AMD Fiji, the first GPU to use HBM.
The development of High Bandwidth Memory began at AMD in 2008 to solve the problem of ever increasing power usage and form factor of computer memory. Amongst other things AMD developed procedures to solve the die stacking problems with a team led by Senior AMD Fellow Bryan Black. Partners from the memory industry (SK Hynix), interposer industry (UMC) and packaging industry (Amkor Technology and ASE) were obtained to help AMD realize their vision of HBM.[17] High volume manufacturing began at a Hynix facility in Icheon, Korea in 2015.

HBM has been adopted as industry standard JESD235 by JEDEC as of October 2013 following a proposal by AMD and SK Hynix in 2010.[4] The first chip utilizing HBM is AMD Fiji which was released in June 2015 powering the AMD Radeon R9 Fury X.[18][2][19]

HBM2 was accepted by JEDEC as standard JESD235a in January 2016.[5] The first GPU chip utilizing HBM2 is the Nvidia Tesla P100 which was officially announced in April 2016.
 
Wiki....

I find it funny that a company that cant even create a memory controller should be the developer.
Just shows AMD way more competent than Intel and others in coming up with new technology and getting it implemented. Can't create a memory controller :LOL:, no need to go there.
 
Just shows AMD way more competent than Intel and others in coming up with new technology and getting it implemented. Can't create a memory controller :LOL:, no need to go there.

See my edited post. AMD isn´t even mentioned in the source for the wiki.

So try again. :)
 
See my edited post. AMD isn´t even mentioned in the source for the wiki.

So try again. :)
Trivial and once again who cares if AMD is mentioned or not - HBM was started by AMD and finished with AMD. Anyways the bigger question is who is Samsung making this rather fast HBM2 memory for? Nvidia already has their Volta V100 designs down, AMD? someone else? Since production has started who is going to use it???

My best guess is the refreshed Vega 12nm cards coming up.
 
Trivial and once again who cares if AMD is mentioned or not - HBM was started by AMD and finished with AMD. Anyways the bigger question is who is Samsung making this rather fast HBM2 memory for? Nvidia already has their Volta V100 designs down, AMD? someone else? Since production has started who is going to use it???

My best guess is the refreshed Vega 12nm cards coming up.

Then why you claim it? :)

FPGAs for once. And dont you mean "7nm" Vega cards? But that's far away,


 
Was coming here to say/wonder the same thing. Might need a different form factor than DDRx DIMMS? One of the things I remember from the original HBM announcements was that it was going to use a ridiculously-wide data bus: hundreds of address lines, not a 64-bit bus as is typical.
If you take HBM off of the interposer the latency would be too much compared to DRAM. HBM system memory would mean no longer being able to upgrade and/or expand without replacing the CPU.
 
That is some serious bandwidth!
Yes but 12 GDDR5 chips working on a appropriately wide bus can go just as fast or faster. The problem is it's much more expensive to design a board with a bus that wide.
 
I know this is mostly aimed at graphics cards, but I do hope samsung has some plans to bring this to system ram.

Due to the way it works, it's not so good with system ram. HBM likes sequential access, not random. And despite what someone claimed earlier, access to HBM does come with a bit of initial latency as it's streamed out serially. However GDDR5 ram has other latency issues due to trace length differences and distance from the core/memory controller.
 
Wiki....

You mean page 118 on this PDF as the source?
https://web.archive.org/web/20150206093927/http://isscc.org/doc/2014/2014_Trends.pdf

I find it funny that a company that cant even create a memory controller should be the developer.
Well seems to me AMD was the FIRST to put a memory controller onto the CPU which kicked intel's rear end at the time.

BUT let me ask you a question....Can you write an algorithm that does better than n-log n on sorting a list? If you say "No" you kind of made my point. Others who make memory controllers have them in such an optimized state and patented, it would be cost prohibitive to design a new one from the ground up that may or may not have a slight advantage. So you just license circuit libraries.
 
If you take HBM off of the interposer the latency would be too much compared to DRAM. HBM system memory would mean no longer being able to upgrade and/or expand without replacing the CPU.

This I agree with. The silicon path traces of the interposer keep the electrons from slowing down. As you transition from one material to another, there are resistive and capacitive differences. Whenever traveling electrons hit this difference, heat is exchanged and there is a partial reflection of current (signal direction) Keeping it a homogenous material from A->Z helps keep bandwidth the same.
 
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Come on folks, AMD/RTG design memory controllers all the time, some just don't know what they are talking about. High bandwidth cache controller is -> A MEMORY CONTROLLER and probably one of the most advanced ones ever design as well. Every AMD/RTG card memory controller, HBM memory controller which was used starting with Fuji was done by AMD (now part of HBM standard) and that design is used as well in Nvidia P100 -> V100. Time to move on.

If Aquabolt is in production -> meaning it is schedule to be bought and used -> Who? and for What?. Unless Nvidia is going to use a configuration similar to Vega, as in a dual stack of HBM2 for their high end gaming Volta cards (very much possible) and keeping the DDR6 for the lower end cards or a mystery design from someone with $ (Apple?) using this high speed HBM2 -> Sounds more like AMD/RTG.

As a note with Vega, mining is mostly limited by memory speeds (severely) and not the GPU compute capability -> So I can see RTG upping their overall compute ability in something, not sure if it would be a gaming card.
 
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