The PCB is likely an ES/dev board. Dev 2080 had 2x8-pin & 2080ti 3x8-pin. It also appears that the chip pad area is larger than TU104. Power draw is any one's guess. Depends on whether they aimed for high transistor density -> more dies/wafer -> lower price.
Edit: Correction.
Marketing slides aside, RT cores are only a dedicated pipeline in the SM with optimized alus/logic & register space/local cache for ray/tris intersection/BVH traversal in parallel with shader ops. The question is, more general purpose "shaders" or additional customized "shaders" at the expense...
There are a number of factors at play with SMPS, but interestingly a key contributor for ripple induced coil whine is the size/value/quality of the primary filtering cap. High quality, adequately specced hold up caps are $$...
Has AMD had much choice since Hawaii? The die was cast with GCN 1.0 uarch wise. Nothing wrong with their bet on resource/die size/allocation tradeoff, they just weren't able to financially sustain development. Esp given perf/watt issues cf paxwell. NV bet on SFU at the cost of silicon area...
Recidivist revisionism...
RIVA TNT and 32 bit 3D color -> Rendition Verite
Geforce 256 and T&L -> Rendition Pinolite et al -> DX7
Geforce 3 and Shaders -> You mean register combiners? -> DX8
Geforce FX and Shader Model 2.0 -> You're shitting me? Register combiners #2 with abysmal performance &...
The issue may be related to silicon lottery variation, not HMB2 as such. Some boards are OK, others exhibit greater variability. Tensor workflow won't suffer given reduced precision & accumulate.
As it stands now, no. In this example Nvidia has now co-opted ROG for itself. There will be no ROG sub-brands for other IHVs. Asus development of ROG branding is constrained. They can develop a new brand or not brand or use the ASRock relationship for AMD "Gaming" cards - they've chosed the...