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  1. J

    Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

    https://fuse.wikichip.org/news/4795/arm-launches-new-neoverse-n2-and-v1-server-cpus-1-4x-1-5x-ipc-sve-and-armv9/ New cores with better microarchitectures, new instructions (including SVE), and adapted to new process nodes. The N2 is an evolution of the N1 used by Amazon and others. The V1 is a...
  2. J

    Qualcomm Completes Acquisition of NUVIA

    https://www.qualcomm.com/news/releases/2021/03/16/qualcomm-completes-acquisition-nuvia Is the Apple M1 competitor coming? Also the announcement does not mention servers, which was Nuvia original target.
  3. J

    Pushing the boundaries of performance and security to unleash the power of 64-bit computing

    Arm highlights its next two generations of CPUs, codenamed Matterhorn and Makalu, with up to a 30% performance uplift. Matterhorn (Cortex-A79?) will be the last to support the 32-bit ARM ISA and the next big cores, like Makalu, will support only the 64-bit ISA...
  4. J

    AMD 64-core EPYC clock speeds leaked - The power of ROME

    https://www.overclock3d.net/news/cpu_mainboard/amd_64-core_epyc_clock_speeds_leaked_-_the_power_of_rome/1
  5. J

    AMD EPYC Rome 32-Core CPU Specs Leaked: 1.7 GHz Base, 2.4 GHz Boost

    https://www.tomshardware.com/news/amd-epyc-rome-32-core-cpu-specs,39373.html Info obtained from qualification sample spotted in SiSoft database. This is a qualification sample, not an engineering sample. So clocks are either final or 100MHz away from clocks of commercial chips.
  6. J

    Hot Chips program is out (IBM Power10, AMD Zen 2 & Navi, ARM Neoverse N1,...)

    http://hotchips.org/program
  7. J

    Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

    https://fuse.wikichip.org/news/2318/ice-lake-brings-a-new-cpu-gpu-ipu-and-i-os-to-follow-by-tiger-lake-next-year/ Both Tiger Lake and Arctic Sound (Intel’s discrete client graphics solution) are back from the fab. 7nm Xe GPGPUs will launch in 2021. A small mistake: contrary to what says the...
  8. J

    2019 Investor Meeting: Intel Previews Design Innovation; 10nm CPU Ships in June; 7nm Product in 2021

    10nm Process Technology: Intel’s first volume 10nm processor, a mobile PC platform code-named “Ice Lake,” will begin shipping in June. The Ice Lake platform will take full advantage of 10nm along with architecture innovations. It is expected to deliver approximately 3 times faster wireless...
  9. J

    AMD publishes Zen 2 compiler patch, exposing some new instructions

    https://phoronix.com/scan.php?page=news_item&px=AMD-znver2-GCC-Patch Short resume: no AVX512 and some new instruction as WBNOINVD (which is an Icelake new instruction).
  10. J

    Intel kills 10nm (rumor)

    https://www.tweaktown.com/news/63592/intel-reportedly-kills-off-upcoming-10nm-process/index.html
  11. J

    Zen L3 IPC

    Raven Ridge CCX has half the cache of its CPU brothers. Anyone knows how much it impact IPC?
  12. J

    Intel’s Plans for 3DXP DIMMs Emerge

    https://www.realworldtech.com/intels-3dxp-dimms/
  13. J

    Intel's desktop marketshare in Mindfactory.de

    Despite all the hype and biased reviews, CoffeeLake and Skylake-X are selling very well even in pro-AMD stores
  14. J

    Fujitsu Completes Post-K Supercomputer CPU Prototype, Begins Functionality Trials

    http://www.fujitsu.com/global/about/resources/news/press-releases/2018/0621-01.html The post-K prototype will be exhibited at ISC 2018, which will be held in Germany from June 24--28. (48 + 2) or (48 + 4) cores per node, built on top of ARMv8 ISA plus SVE extensions (implemented with 512bit...
  15. J

    Intel tipped to launch discrete GPU at next year's CES

    https://www.theinquirer.net/inquirer/news/3032131/intel-tipped-to-launch-discrete-gpu-at-next-years-ces The rumor is that Intel has been working in the GPU during two years and could launch it in January 2019. What I would like to know is if this will be only a dGPU on package (KBL-G style) or...
  16. J

    AMD also affected by Spectre Next Generation?

    Intel and ARM were confirmed time ago, but no word on AMD. Now comments on a kernel fix seem to confirm AMD is affected as well http://anzwix.com/a/DragonFlyBSD/Kernel - Fix CVE-2018-8897, Debug Register Issue
  17. J

    Spectre Next Generation

    Eight new vulnerabilities found on Intel processors https://www.ghacks.net/2018/05/03/spectre-next-generation-vulnerabilities/
  18. J

    Jim Keller joins Intel

    https://www.pcper.com/news/Editorial/Jim-Keller-Leaves-Tesla-Intel It seems the dream team is joining Intel. First Koduri now Keller... His work could be related to "Ocean Cove" core project https://www.fool.com/investing/2018/04/25/intel-corp-wants-to-build-a-revolutionary-processo.aspx
  19. J

    Up to 64 core EPYC 2 CPU

    https://hothardware.com/news/amd-epyc-2-64-cores-128-threads-and-256mb-l3-cache It seems my prediction of 6-core CCX for Zen2 has been just killed. Either AMD is going for 8-core CCX modules or will maintain the same 4-core configuration and will add four CCX modules per die. I think 8-core...
  20. J

    AMD Transtioning To 12nm LP Process For Vega, Ryzen In 2018

    14LPP+ has been replaced by renamed to 12LP http://www.tomshardware.co.uk/amd-ryzen-vega-12nm-lp-2018,news-56797.html http://wccftech.com/amd-announces-2nd-gen-ryzen-vega-launching-12nm-2018/ EDIT: Toms mentions 14nm, but Glofo is really using TSMC 16nm as baseline Note that a true 16nm...
  21. J

    HP workstations powered by Skylake Xeon

    Advertised as the most powerful workstation in the planet http://www.anandtech.com/show/11838/hp-updates-z8-workstation-up-to-56-cores-3-tb-ram-9-pcie-slots-1700w
  22. J

    Skylake Xeon benches

    The Xeon thread was closed, therefore I am posting this stuff here
  23. J

    Some Ryzen Linux Users Are Facing Issues With Heavy Compilation Loads

    https://www.phoronix.com/scan.php?page=news_item&px=Ryzen-Compiler-Issues It originally looked as an bug on GCC, but last research seems to confirm this is part of the older SMT/uop bug. Remember that earlier engineering samples had uop or the SMT disabled due to this bug. It seems that the bug...
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