Sanctions are nothing compared to the accelerated transformation of the energy sector of western europe. The war was a wake up call forcing them to modernize their infrastructure. It will never be the same. There will never be the same market for energy again. Russia cam lean on china but even...
The problem is with the specifications and overclocking categories. They list many factors that go either way then draw a conclusion that intel wins.
For one overclocking is now the power budget. Yes intel has a much higher budget and AMD is nothing but diminished returns. But intel already...
Being a 5800x -> 5800x3d* owner who basically side graded into it. I'm ok with it. Moar power to the AM4**. I never buy into a new socket. Never say never***
* i give my cast offs to friends and family
** AM4+ asking for a friend
*** Romeo Void not that Bieber carp
I don't know if you compensated for it but.
If your Kill A Watt is pulling 700w your components are pulling 80-85% x 700w = 560-600w. Even less if you measured upstream of your UPS.
2 pumps + 15 fans is a lot of stuff but still under 100w.
I stopped using a ups because, at least the few I've...
It looks really neat.
The new mesh
12 x 12 = 144
6 x 6 = 36
Which I guess implies each 72 core chip is a 6 x 6 mesh. 2 cores per cross point 2 x 6 x 6 = 72
Further a 4 chip module would be 4 x 2 x 6 x 6 = 288
So CMN-700 is 4 x CMN-600 how nicely incremental
I went through almost everything I've seen and it's slim pickings, literally, other than a few that are specifically made for body image. (Ex Princess Jellyfish).
Black Clover does have some.
Charmy dark hair below. (although Charmy has many forms)
Fire Force. Maki Oze. Turn...
I kindo like the new Faye. IMO she was way too brooding in the original. Yeah her story was super tragic, but she seems fun now.
I felt the original Wild Wild West segways in that new teaser.
Maria Murdock near the end, they sure prettied her up. It's an outrage. Yes I'm being sarcastic
The Ampere Altra Max Review: Pushing it to 128 Cores per Socket
Very unique. Moar Cores / Moar Problems.
TLRL: Less L3, cache coherency rears its head, throughput for some things is amazing as is compiling (not linking), transactional java sux.
I have no problem with the casting.
Jet was voiced by a black man (Beau Billingslea) back in the day and for someone who loves the voices of DUB anime the new casting fits. When I hear him in other anime. Ex Rom in "Zero, Starting Life in Another World", I declare that's Jet. He's old now, so...
It does make you wonder. AMD's L3 latency went up, Zen 2 40, Zen 3 46. Maybe just to get better clocks. Or maybe extra logic to work with memory stacked on top of it.
Does the cache line increase to 192 or way to 48 ?
I see a bit of convergence happening here. The latest neoverse and it's MPAM (memory partition and monitoring) show that with large scale processors, housekeeping is more than necessary. The ampre did a great job of prioritizing non-streaming loads memory access, which seemed to allow it to keep...
By logical fallacy ?
Arguing that because something is changed now it suddenly erases the past only proves you are lazy and refuse to read the article.
Technically taking a screenshot out of context isn't arguing but go forth and pwn nubs...
Ok stop defending them so virulently
Straw man. I have problems with anti-competitive behavior. Stop trying to re-frame it, they applied 2 different standards to competing products. I assume they have one checkout software, and by extension, would have to specifically design rules to create a...
I have no problem with EVGA or any supplier's choice to carry a product. (As long as they don't pull a Sapphire scalping) I have a problem with non-competitive behavior.
If you're so savvy in tech and sales, why are you acting as an apologist for Dell? Convoluting the issue with weird anecdotes...
So if you went to a dealership that sells both BMW and Hyundai and the sales team was only showing BMWs with eco mode on while the Hyundais were allowed to run in sport, (for whatever reasons) you would be ok with that ?
I think a lot is being missed in this latency focus. DDR5 has a bunch of tweaks that make past metrics less comparable. Each DIMM is dual channel with on board circuitry with ECC and management. I only wonder if this can provide some out of order processing. The ROW latency (above) is only one...
Read the article. Previously ...
Which is why this is good journalism. Shine light fix shit.
woosh (over your head)
The user can't spec single channel 16gb on intel. Yet that is the default on AMD. If default configurations were put head to head, the AMD system would look bad.
Moreover, if one were to take those default systems and look them up on a piece of shit propaganda site like...
In this modern, media driven culture, where exact specifics are listed as a badge of honor and not a least common denominator, such disparities are unacceptable.
Kudos to extreme for compiling and shining light on this piece of shit activity. Anything less than a public apology from Michael S...
I've had the privilege of wandering Fry's more than a few times around the turn of the century. (Palo Alto) Now that I'm on the other coast. I've gone out of my way to support my local Micro Center. Man they've come and gone. Rad Shack, CompUSSR, Frys, don't take the last one...
Insanely well written article. Andrei did such a good job of pointing out the various differences and tying them into the outcomes. Icing on the cake was the explanation for the high memory numbers.
Ampere did so many unique things. 64k pages, memory controller provisioning (4x2chan), very...
M1 was a poor choice to compare with. It over preforms as a 4+4 and under performs as an 8. It is possibly the furthest point of reference sans a mid range quad core. A 4800u scores ~10k which is ~8x the ~80k+ result. (cinebench nice scales)
But I can see why the latest buzz needs to be...
I don't do this crap but I know there are some CPU-ID stuff you can do to mitigate problems during movement of VMs up and down the compatibility tree. It really sounds like you're just lazy or unwilling learn.
Strong Memory order died with the 486. Everything past then must use specific instructions to control the order (locks, fences/barriers, flushes).
From intel's own manual (here) sec 8.2.1
Moreover, there are a lot more specifics to how a modern x86 can control memory and instruction order...