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Yea, it was. Meant to put it from the first EX to the second. I just meant... there's two MUX going into the same ALU, each with a blue line in from the forwarding control unit. So I assumed that one was for controlling if the value came from the rt register or was forwarded instead if needed...

I've just finished trying this problem from my book but there's no answer key and I'm not fully sure and would like to know if I've done it correctly, or am overlooking something. I'm assuming MUX is for determining the rt value and the other rs? Is that correct?

"So in the first set the only potential hazard is between 1st instruction and 3rd instruction. My answer still applies, but the value forwarding part isn't necessary as the 1st instruction will have already written to the destination register by the time the 3rd instruction needs it." Wait...

I'm going over pipelining and stalls and forwards with MIPS architecture, and there's a couple things I'm uncertain about. If two adjacent instructions, such as the first two of each set bellow, both use the same register, but the first isn't actually modifying that register, is there still a...

Thanks, I'll check it out.

Thanks. *sigh* for the price of these books it would be nice if they'd at least make sure all their problems make sense...

I am doing book problem that wants translated MIPS assembly to matching C++ lines. it gives: k = $s0, A[] base address = $s7 addi $t0, $s7, 4 add #t1, $s7, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0 my attempt to solve what it doing: t0 = &A[1] t1 = &A[0] 0(t0)/A[1] = &A[0] ?? t0 =...