They just FIT. No trimming required. Like a conspiracy or something...
Both are metric, 48" is only...
There is nothing to be found inside those PS/2 converters, all the magic (or not) is in the keyboard.
Most USB keyboards retain fallback capability to PS/2 over USB, just so those converters can work.
I've searched high and low for a PS/2 keyboard in good condition to connect with Pi Pico's...
I'm trying to hack a VGA cable with some resistors, as the latest beta theoretically supports.
Thinking maybe I can stuff this all inside an old PS/2 keyboard. Without pins, its fairly small.
By default or...
Another useless development, the "impossible" asynchronus XOR gate in 555...
One input mixer simultaneously compares against different references with opposing results.
References differ by about 1 vote. XOR ( A , B ) = AND ( MAJ3 ( A , B , 0 ) , MIN3 ( A , B , 1 ) )
THRS has been set just...
The above plan was doomed. Because it allowed signal to propagate any time after reset, it doesn't hold back to one predictable forward step.
Like syncronus if logic happens to tip one way, asynchronus the other. Yeah, completely broken.
So what might fix this? Vote time (blue) should be...
Back to Majority logic for a moment...
No clue if this would actually work, only got 4 of these ICs in my junk drawer.
Coincidentally, Digikey is running some sort of a most useless 555 challenge.
I've got till Jan 10th to embarass myself, maybe not impossible.
One very slow bit at a time here...
And I just had another useless revelation
while staring too long at this damn borrow
and magnitude chain.
Invert: borrow in, borrow out, result out.
Another way to mutate A-B to B-A when
subtracting. Should work for other ALUs.
As relates to my ALU: I've got two new
subtraction functions to...
Though a caption originally attatched to news photo said like 1.5GByte per 8.8mm square.
How exactly that figures to 500TB? Best check the math, cause I only extrapolate 193GB
from a 10cm square without gaps. Something about this article doesn't smell accurate...
An issue of all my prior drawings was the very thin chain of single pass
gates driving cumulative fanout of inactive passages and XOR inputs.
Capacitance multiplied by 16bit length could become a real problem.
Main features of this drawing are parallel passages for the critical path.
Photo shows a mix of SSOP and TSOP parts on the front.
For the moment, nothing but empty SOIC pads exist on back.
Individual slices need some wires between those SOIC pads.
Complete assembly might look like eight books on a DIP40 shelf.
A floppy pigtail might bring in power better than rely on...
I found my old stash of 74S86 XORs. 5v, power hungry, faster than average,
already DIP, won't need any adaptors. Fine for testing wether the plan gives
correct math results. Speed of carry chain measurement won't be affected.
3relay will definately replace 5relay for the demo box with vintage...
In you wonder how MUX logic evolves from relay logic:
Keep in mind that Voltage difference across a coil performs XOR.
Diode bridges aren't XOR, but to keep coils from throwing sparks.
Though seems a waste to use only SPDT as the final full adder.
Was more important to show same as possible...
Also reading about a strange MUX family that strengthens pass-logic by pulling up signals
that are already over half. I dunno if thats a good idea or not, what keeps it from latching?
One of these every byte or so might allow for a very long carry chain, but might also dumb
things down to a...
Completely unchanged circuit, only better documented.
74AUC2G86 spec at 2nS per gate. A pair should be faster than 6nS 74CBT3251 they replaced.
XOR XNOR are used by addition. Redundant NXOR' XOR' fix subtraction's inverted borrow.
Same exact functions, slightly different control scheme. Only...
Carry chain done. Flow is from top to bottom.
Those beefy wires are scavenged from CAT5. Dunno what happened
to my roll of blue Kynar, probably find it after I'm done. Kynar doesn't
melt quite so easy or shrink back from where it was cut.
This was an absolute mess, too tiny to get right...
Truth table side done and partially cleaned.
These aren't gateless. I havn't forgot about gateless, just not what this is.
FPGA do not offer transmission gates required for an instant pass-through
carry chain. Header pins are way too thick for SOIC spacing, already tried.
I have plenty of...
Just tried that. Wired columns are a disaster.
Way too fiddly trying to hold it all straight.
Even abusing the breadboard to hold the
other end stationary.
Need a stereo microscope and extra hands.
Maybe if I superglued the chips together
instead of relying entirely on tacky flux that
Well, that sux. Even folded down to look like DIP, SOIC pins
aren't long enough to touch the next chip underneath. What
do I do to fix this? Sand bottoms and tops before bending?
Or I gotta lay an actual wire down each connected column?
Or I could put each on an adaptor board before stacking...
Might pile them up in stacks of four, something like this...
Least significant bit on top, Most significant on bottom.
Each pile would need a supporting pair of 74S86 quad XOR.
Maybe later, a faster quartet of 74LVC2G86 or 74AUC2G86.
Ditching ALU MUX(A,B) capability, which there are several other ways to implement.
This allows a greatly simplified control scheme. A single Manchester Carry chain is
bent (by inverting B) to handle subtraction and magnitude. Chain wiring can happen
all on one physical side of the SOIC package...
Lets talk decoding for a moment. How to reduce the number of control lines required?
4way multiplex allows lookup of 16 possible truths. Each representing a two input - one output logic function.
Now I propose we separate two basic groups of those functions: The useful group and the weirdo...
Needs power, ground, decoder. Lights and switches not a priority. May skip decoding and let an arduino begin checking wether direct control even works.
LSB is on the right. SUB was wired as the alternate chain, rather than ADD. Otherwise mostly per last posted drawing.
Hope to piggybug at least...
BNC also a plenty cheap standard barrel...
Survey says prolly no good beyond 500W.
And thats not taking into account 50V limit
might necessitate extra current. If its never
going over 5A, BNC pin might handle that.
Both ends should measure roughly the
same voltage and exact same current.
Not saying Sandia used parametrons for latching superregenrative amplification.
More likely a non-latching travelling parametric amplification that also mixes as it
goes down the line. Maybe this technique that worked for Stanford...
If absence of an electron can carry heat (as proven by the P blocks in a Peltier cooler), maybe could also carry information?
A phonon of excited electrons around each hole may be the actual carrier. Sounds like someone got that hot mess to swirl.
Ian (not Anand) eventually does address electromigration. Only had to wait a decade or so...
Maybe Anand didn't hear my question properly? I can't properly hear myself in that video.
Went off on...