erek
[H]F Junkie
- Joined
- Dec 19, 2005
- Messages
- 10,875
Some interesting developments and constructs in the Open Chiplet Interface community:
"It’s worth highlighting that BoW is designed for standard multi-chip packages with a bump pitch of around 130-micron yielding a bump density of just 68 bumps/mm². More recently, Intel unveiled the MDIO interconnect which has much more aggressive shoreline bandwidth density. Nonetheless, BoW makes up for it with higher data rates. The final result is that, against the current generation of interconnects, with the ability to stack up to four slices, BoW provides slightly lower areal bandwidth density but higher shoreline bandwidth density."
https://fuse.wikichip.org/news/3199...en-chiplets-interface-for-organic-substrates/
"It’s worth highlighting that BoW is designed for standard multi-chip packages with a bump pitch of around 130-micron yielding a bump density of just 68 bumps/mm². More recently, Intel unveiled the MDIO interconnect which has much more aggressive shoreline bandwidth density. Nonetheless, BoW makes up for it with higher data rates. The final result is that, against the current generation of interconnects, with the ability to stack up to four slices, BoW provides slightly lower areal bandwidth density but higher shoreline bandwidth density."
https://fuse.wikichip.org/news/3199...en-chiplets-interface-for-organic-substrates/