An Interconnected Interview with Intel’s Ramune Nagisetty: A Future with Foveros

Seems to be a lot of interesting information and technologies in this Intel interview

"When it comes specifically to monolithic 3D, it’s entirely possible to do it. The question is going to be of thermal issues as well, so I think you know the key issue when you’re doing die stacking is that we needed to think about our architecture in terms of optimizing for the power efficient corner of where we needed to be, and we’ll gain performance on top of that from adding additional transistors, functionality, and capability with each layer. With a monolithic 3D design, we might not be able to reap that benefit if we continue with a design approach that is focusing on the optimization for the performance end of things."



https://www.anandtech.com/show/1527...intels-ramune-nagisetty-a-future-with-foveros

erek said:

With a monolithic 3D design, we might not be able to reap that benefit if we continue with a design approach that is focusing on the optimization for the performance end of things

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IOW, we may need to scale back clocks (either dynamically or a hard limit) or spread out components in order to prevent hotspots inside the processor from causing damage. This can have performance implications in certain scenarios where latency or heavy cpu use is a concern.

Some of that can be mitigated with smart core utilization and load balancing, but we'll have to wait to see how it turns out in practice.

With a monolithic 3D design, we might not be able to reap that benefit if we continue with a design approach that is focusing on the optimization for the performance end of things.

Click to expand...

So... Intel is going to focus on safety-first computing, unmitigated performance be damned.