Ryzen 3000 will have DDr4-5000 mhz support?!

I agree. Manufactures always seem to OFFICIALLY support a very conservative speed. Now will it do DDR4-5000? Probably. Even first gen Ryzen has gotten to very high DDR4 speeds. I would imagine even Zen+ somewhere has already hit 5000. Zen2 I am imagining has the best most stable memory controller yet.
 
the motherboards might support DDR4 5000 but no way in hell the IMC supports it. even intel's IMC's have issues with it.
 
the motherboards might support DDR4 5000 but no way in hell the IMC supports it. even intel's IMC's have issues with it.
Considering DDR4-5000 is no where near mainstream I as well doubt it. But "No way in hell" is and over-reach for an unreleased chip don't you think? I mean Zen+ is already pushing very high in the hands that know what they are doing.
 
When I see WCCFtech or Adored TV listed as references, I usually just wave it off or go grab the salt shaker.
 
Infinity Fabric has a multiplier on these upcoming chips so that can allow for much higher memory clock speeds in theory.
 
Infinity Fabric has a multiplier on these upcoming chips so that can allow for much higher memory clock speeds in theory.

See this^^

So many people think they know what AMD is doing but like Dozer to Ryzen it was a massive leap.

So Ryzen 1 to ryzen 2 might be a massive leap again.

I'm not paying attention to the peanut galleries with bull horns.

Let me add (edit) that Peanut Galleries with Bullhorns are on both sides is what I meant by that comment.

You got those that say the performance is going to be unlike anything we have ever seen, and yet others saying it is going to be a total flop. The two extreme ends is what I want t avoid.
 
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See this^^

So many people think they know what AMD is doing but like Dozer to Ryzen it was a massive leap.

So Ryzen 1 to ryzen 2 might be a massive leap again.

I'm not paying attention to the peanut galleries with bull horns.

Let me add (edit) that Peanut Galleries with Bullhorns are on both sides is what I meant by that comment.

You got those that say the performance is going to be unlike anything we have ever seen, and yet others saying it is going to be a total flop. The two extreme ends is what I want t avoid.

I agree, just keep your expectations sane. You'll either be pleased to have them met, or amazed at how far they are surpassed.
 
I agree, just keep your expectations sane. You'll either be pleased to have them met, or amazed at how far they are surpassed.


I mean at a minimum the new chips are going to absolutely surpass the older chips. Thats a given minimum. The architecture is not a new design from scratch, like Ryzen was compared to Bulldozer in fact, it is the same architecture with significant improvement to process, die layout, memory controller, and a host of other things. How can it possibly be worse than Zen + cores?
 
Just curious about high core count (12 & 16 cores) Ryzen & & 8 CPUs and the dual-channel memory they are limited by...?
 
I mean at a minimum the new chips are going to absolutely surpass the older chips. Thats a given minimum. The architecture is not a new design from scratch, like Ryzen was compared to Bulldozer in fact, it is the same architecture with significant improvement to process, die layout, memory controller, and a host of other things. How can it possibly be worse than Zen + cores?

In this particular response, I was only speaking toward the RAM controller and the speeds mentioned by the OP.

I agreee that Ryzen 2 should surpass the Zen+ (if it didn't then what's the point), but then again there's the Vega launch... I'm sure the Zen 2 chips will be great, either in time, or right from launch.
 
Biostar board release yesterday showed max DDR4 4000. So I wouldn't expect 5000. Maybe on some super fancy RoG beast.
 
I expect a 20% improvement at the same pricepoint. There may be some outliers in each direction (big gains here, no improvement there..)
The increase in selection and features (16 core count non-TR chips, PCIe 4.0 and more ports, etc.) will be nice. I hope the memory support and latency have been an area of focus, and given the confidence to include a 16 core chip in a dual channel format, it better be. Dual channel at 4000-5000 mhz on a Ryzen 3000 could close the gap to TR1 with its less efficient off-cluster memory access issues, for example.
 
You'll get faster ram, but 5000 is no way. This just means they put in the bios hooks for it, woop de doo.

The one major change that will help is the fabric speed will have non 1:1 divider options vs ram speed which should open up the wall currently in the low 3000s for pretty much every Zen chip out there. The IMC is moving to the I/O die as well which a pretty big unknown, we will find the new wall once people actually have chips in hand. Right now its nothing but speculative bullshit out there.

It will likely still require good kits to get decent speeds (b-die, maybe the newer stuff), but perhaps it won't be as picky as before with inferior ICs.
 
You'll get faster ram, but 5000 is no way. This just means they put in the bios hooks for it, woop de doo.

The one major change that will help is the fabric speed will have non 1:1 divider options vs ram speed which should open up the wall currently in the low 3000s for pretty much every Zen chip out there. The IMC is moving to the I/O die as well which a pretty big unknown, we will find the new wall once people actually have chips in hand. Right now its nothing but speculative bullshit out there.

It will likely still require good kits to get decent speeds (b-die, maybe the newer stuff), but perhaps it won't be as picky as before with inferior ICs.

So Samsung has ceased B die fabrication.

They are now producing A die but I dont know what A die means compared to B.
 
And next year is the last year that AM4 is around makes it doubtful that it is a good investment.
 
And next year is the last year that AM4 is around makes it doubtful that it is a good investment.

AMD has stated that they will support the AM4 socket until 2020, not thru 2020...

And there are rumors of Zen 3 being a 2020 product, so AM5 sockets in late 2020, with PCIe 5.0 & quad-channel DDR5...?
 
AMD has stated that they will support the AM4 socket until 2020, not thru 2020...

And there are rumors of Zen 3 being a 2020 product, so AM5 sockets in late 2020, with PCIe 5.0 & quad-channel DDR5...?

Quad channel would raise the cost of the motherboards to much. There is a Zen 3 video out by Adoredtv and Moore's law is dead on youtube. But it is a big picture point of view hardly anything concrete.

I'm not to sure where you are getting your PCIE 5.0 from. Since 4.0 is not even here officially.

Look at it this way for quad channel memory to be needed you need to be able to saturate the memory bus in all applications and as long as that is not happening something as an enthusiast platform with better memory bandwidth and more PCI-E lanes will have grounds to exist.

If not this would be a waste of money producing boards that have no functionality beyond bragging rights.
 
AMD has stated that they will support the AM4 socket until 2020, not thru 2020...

And there are rumors of Zen 3 being a 2020 product, so AM5 sockets in late 2020, with PCIe 5.0 & quad-channel DDR5...?

There is like a 1% gain in quad channel. We just need really really fast dual channel honestly.

I have quad now and I get like 5 fps more in h265 encoding so not alot.
 
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Quad channel would raise the cost of the motherboards to much. There is a Zen 3 video out by Adoredtv and Moore's law is dead on youtube. But it is a big picture point of view hardly anything concrete.

I'm not to sure where you are getting your PCIE 5.0 from. Since 4.0 is not even here officially.

Look at it this way for quad channel memory to be needed you need to be able to saturate the memory bus in all applications and as long as that is not happening something as an enthusiast platform with better memory bandwidth and more PCI-E lanes will have grounds to exist.

If not this would be a waste of money producing boards that have no functionality beyond bragging rights.

One thing that could make use of a lot more memory bandwidth is an improved APU.

Memory BW is a significant bottleneck on future APU performance.
 
One thing that could make use of a lot more memory bandwidth is an improved APU.
Memory BW is a significant bottleneck on future APU performance.

So could HBM and there prolly more options but none of them make sense because the only market there is for APU is semi custom consoles and they solved their own problems :) .
That leaves the laptop market when is the last time you seen serious efforts to increase memory performance on such devices?
They tend to skip on that part and have dedicated gpu with dedicated memory. And the only thing that would make sense in that regard is HBM based APU and that would put a serious dent into the consumers wallets.
 
So could HBM and there prolly more options but none of them make sense because the only market there is for APU is semi custom consoles and they solved their own problems :) .
That leaves the laptop market when is the last time you seen serious efforts to increase memory performance on such devices?
They tend to skip on that part and have dedicated gpu with dedicated memory. And the only thing that would make sense in that regard is HBM based APU and that would put a serious dent into the consumers wallets.

The whole point is to get more GPU performance from the APU so you don't need the dedicated GPU as often. The combination of Triple channel DDR5 might be a reasonable compromise, that would add a nice boost to APUs, so they can move a little further up the chain.
 
The whole point is to get more GPU performance from the APU so you don't need the dedicated GPU as often. The combination of Triple channel DDR5 might be a reasonable compromise, that would add a nice boost to APUs, so they can move a little further up the chain.
That did not escape me, just that your solution requires a lot of extra hardware features (cpu support for more then 2 channels) and motherboards to solve that problem.

If there was such a feature needed for APU then HBM would be better and cost effective. Rather then design a whole new platform.
 
That did not escape me, just that your solution requires a lot of extra hardware features (cpu support for more then 2 channels) and motherboards to solve that problem.

If there was such a feature needed for APU then HBM would be better and cost effective. Rather then design a whole new platform.

They ought to make hbm sticks for motherboards woot woot

Imagine 32GB of HBM ram.
 
That did not escape me, just that your solution requires a lot of extra hardware features (cpu support for more then 2 channels) and motherboards to solve that problem.

If there was such a feature needed for APU then HBM would be better and cost effective. Rather then design a whole new platform.

As far as cost effective. HBM is more expensive than DDR, and you probably need a new larger socket to fit it in as well.

Besides DDR5 is likely when the redesign for AM5 socket anyway.

With AMD pushing high core counts on mainstream, if they are designing a new socket to carry them another 4 or 5 years it seems like another memory channel might be a sound idea, unless 16 core is where they stop.
 
They ought to make hbm sticks for motherboards woot woot

Imagine 32GB of HBM ram.

True :) but so far you might be able to offload the HBM on the IO die as a cache not as a replacement for DDRx :)
I did not mention this sooner. But you could speculate that with Ryzen 3000 such features where you have place for more then one chiplets you could also think of the IO die as multi purpose ....
 
Cache only does so much. You still need the bandwidth, especially for graphics. A third memory channel is small incremental cost, that can provide a 50 percent boost in memory bandwidth.
 
After two different consoles with GDDR5 for a combined system and GPU ram pool, as well as a Chinese windows 10 based pseudo console with the same architecture, I’d strongly consider a mobo with 16GB soldered GDDR5 and a SOC that took advantage of it.
Triple channel is another option too that’s more expensive and still slower but more flexible.
I’ve only seen triple channel and up on HEDT platforms that are shared with servers due to the added cost and complexity. The engineering and validation on a small number of motherboards would probably be as much or more than the added mfg. cost. Maybe an APU based on thread ripper 2.
 
After two different consoles with GDDR5 for a combined system and GPU ram pool, as well as a Chinese windows 10 based pseudo console with the same architecture, I’d strongly consider a mobo with 16GB soldered GDDR5 and a SOC that took advantage of it.
Triple channel is another option too that’s more expensive and still slower but more flexible.
I’ve only seen triple channel and up on HEDT platforms that are shared with servers due to the added cost and complexity. The engineering and validation on a small number of motherboards would probably be as much or more than the added mfg. cost. Maybe an APU based on thread ripper 2.

What do you mean Triple channel DDR is more expensive? Not more than GDDR like the consoles. PS4 for instance uses GDDR AND a Quad Channel bus.

You have only seen triple channel on HEDT, because it was only needed on HEDT, but with 16 cores going mainstream on AM4, and who knows how far beyond that on AM5, it makes sense that the next generation platform is really going to to need that memory bandwidth as much as, if not more than older generation 3 channel HEDT did.

I am not saying it is going to happen, but it shouldn't be a surprise if it does.
 
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They ought to make hbm sticks for motherboards woot woot

Imagine 32GB of HBM ram.
Part of the appeal of HBM ram is that it uses a very wide bus and you use it with a high density interconnect like a silicon interposer/EMIB where running a 1000bit bus is not too difficult. Running 1000 signals through a regular PCB and sockets/slots is not cheap/feasable. I'm also not certain if it was designed to run longer distances.

In those cases its better to run a few extremely high frequency serial signals (pcie, ddr, etc).
 
Part of the appeal of HBM ram is that it uses a very wide bus and you use it with a high density interconnect like a silicon interposer/EMIB where running a 1000bit bus is not too difficult. Running 1000 signals through a regular PCB and sockets/slots is not cheap/feasable. I'm also not certain if it was designed to run longer distances.

In those cases its better to run a few extremely high frequency serial signals (pcie, ddr, etc).

Or 3d stack 32gb of level 3 cache on the top of the CPU dies. No need for ram anymore.
 
Or 3d stack 32gb of level 3 cache on the top of the CPU dies. No need for ram anymore.

Likely an even more expensive/difficult option than the Interposer AMD is currently using, or they would be doing it already for GPUs.
 
Likely an even more expensive/difficult option than the Interposer AMD is currently using, or they would be doing it already for GPUs.

They are all planning to do this as there is no further road map for silicon based performance gains. Read up on AMD and Intel on 3d stacking.
 
They are all planning to do this as there is no further road map for silicon based performance gains. Read up on AMD and Intel on 3d stacking.

You mean no more density improvements? Because chip stacking improves density, but really doesn't aid performance.

As far as density:

7nm -> 5nm -> 3nm are all major nodes in the cards, so we are many years before we hit any kind of wall.
 
You mean no more density improvements? Because chip stacking improves density, but really doesn't aid performance.

As far as density:

7nm -> 5nm -> 3nm are all major nodes in the cards, so we are many years before we hit any kind of wall.

Chip stacking the cache was a whole subjwct discussed. Essentially increasing performance hundreds of percent.

3nm may not be achievable. I mean the valence shell of an Si atom is arpund 0.3nm but it takes several atoms to make an transistor function. Add in the doped phosphorous atoms and the size increases substantially. Thus I'm not sure how we are going to reliably control the unpredictable quantum effects at these micro sizes. Add in the fact that due to transistors at these small sizes, 3nm, how can we reliably control factors like covalent bonding etc if other impurities further intensify the already incredibly tight tolerances at such a small nuclear sized process.

While I only have a minor in Chemistry and a minor in physics I know enough that anyone who suggests that we would go smaller than 5nm or 3nm for that matter probably just repeating internet forum jibber. Not poking at you. What you suggest for now is in the cooking pot by the fans. I'm talking about hitting the limits of dope silicon.
 
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Chip stacking the cache was a whole subjwct discussed. Essentially increasing performance hundreds of percent.

Actually you were talking about replacing the entirety of System RAM.

3nm may not be achievable. I mean the valence shell of an Si atom is arpund 0.3nm but it takes several atoms to make an transistor function. Add in the doped phosphorous atoms and the size increases substantially. Thus I'm not sure how we are going to reliably control the unpredictable quantum effects at these micro sizes. Add in the fact that due to transistors at these small sizes, 3nm, how can we reliably control factors like covalent bonding etc if other impurities further intensify the already incredibly tight tolerances at such a small nuclear sized process.
.

The Names of a process have very little connection with the actual physical size of features.

Samsung seems well on it's way to 3nm. They already have an early design kit to share with customers:
https://hardforum.com/threads/anandtech-samsung-announces-3nm-gaa-mbcfet-pdk-version-0-1.1981638/
 
While extra bandwidth may be beneficial for a 16 core CPU triple channel and quad channel comes at the price of higher latency which is why Intel 2011 platform is slower for games than 1151 despite extra memory bandwidth, It is a big part of the reason why Ryzen falls behind 1151 and why Threadripper is slower for games than Ryzen.
 
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